A high throughput LDPC decoder design based on novel delta-value message-passing schedule

Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journalArticle

Abstract

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard targeting high throughput applications. The proposed decoder has several merits: (i) The decoder is designed based on a novel deltavalue based message passing algorithm which facilitates the decoding throughput by redundant computation removal. (ii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder can achieve 8 times increasement in throughput, reaching 418 Mbps at the frequency of 200 MHz.

Original languageEnglish
Pages (from-to)122-130
Number of pages9
JournalIPSJ Transactions on System LSI Design Methodology
Volume2
DOIs
Publication statusPublished - 2009

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Message passing
Throughput
Sorting
Decoding

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

A high throughput LDPC decoder design based on novel delta-value message-passing schedule. / Ji, Wen; Li, Xing; Ikenaga, Takeshi; Goto, Satoshi.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 2, 2009, p. 122-130.

Research output: Contribution to journalArticle

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