A highly efficient inverse transform architecture for multi-standard HDTV decoder

Hang Zhang, Peilin Liu, Yu Hong, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.

    Original languageEnglish
    Title of host publicationASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
    Pages525-528
    Number of pages4
    DOIs
    Publication statusPublished - 2009
    Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
    Duration: 2009 Oct 202009 Oct 23

    Other

    Other2009 8th IEEE International Conference on ASIC, ASICON 2009
    CityChangsha
    Period09/10/2009/10/23

    Keywords

    • Architecture
    • AVS and MPEG1/2/4
    • Distributed arithmetic
    • H.264/AVC
    • Inverse transform

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Zhang, H., Liu, P., Hong, Y., Zhou, D., & Goto, S. (2009). A highly efficient inverse transform architecture for multi-standard HDTV decoder. In ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC (pp. 525-528). [5351634] https://doi.org/10.1109/ASICON.2009.5351634