A highly parallel architecture for deblocking filter in H.264/AVC

Lingfeng Li, Satoshi Goto, Takeshi Ikenaga

Research output: Contribution to journalArticle

29 Citations (Scopus)

Abstract

This paper presents a highly parallel architecture for deblocking filter in H.264/AVC. We adopt various parallel schemes in memory sub-system and datapath. A 2-dimensional parallel memory scheme is employed to support efficient parallel access in both horizontal and vertical directions in order to speed up the whole filtering process. This parallel memory also eliminates the need for a transpose circuit. In the datapath, an algorithm optimization is performed to implement parallel filtering with hardware reuse. Pipeline techniques are also adopted to improve the throughput of filtering operations. Our design is implemented under TSMC 0.18 μm technology. Results show that the core size is 0.82 × 1.13mm 2 when the maximum frequency is 230 MHz. Compared to other existing architectures, our design has advantages in both speed and area.

Original languageEnglish
Pages (from-to)1623-1628
Number of pages6
JournalIEICE Transactions on Information and Systems
VolumeE88-D
Issue number7
DOIs
Publication statusPublished - 2005 Jul

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Parallel architectures
Data storage equipment
Computer systems
Pipelines
Throughput
Hardware
Networks (circuits)

Keywords

  • Adaptive filter
  • Deblocking filter
  • H.264/AVC
  • Parallel memory

ASJC Scopus subject areas

  • Information Systems
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

A highly parallel architecture for deblocking filter in H.264/AVC. / Li, Lingfeng; Goto, Satoshi; Ikenaga, Takeshi.

In: IEICE Transactions on Information and Systems, Vol. E88-D, No. 7, 07.2005, p. 1623-1628.

Research output: Contribution to journalArticle

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