A hybrid architecture for efficient FPGA-based implementation of multilayer neural network

Zhen Lin, Yiping Dong, Yan Li, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages616-619
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur
Duration: 2010 Dec 62010 Dec 9

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CityKuala Lumpur
Period10/12/610/12/9

Fingerprint

Multilayer neural networks
Field programmable gate arrays (FPGA)
Neural networks
Topology
Schematic diagrams
Multiplexing
Pipelines
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lin, Z., Dong, Y., Li, Y., & Watanabe, T. (2010). A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 616-619). [5774961] https://doi.org/10.1109/APCCAS.2010.5774961

A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. / Lin, Zhen; Dong, Yiping; Li, Yan; Watanabe, Takahiro.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. p. 616-619 5774961.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, Z, Dong, Y, Li, Y & Watanabe, T 2010, A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 5774961, pp. 616-619, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, 10/12/6. https://doi.org/10.1109/APCCAS.2010.5774961
Lin Z, Dong Y, Li Y, Watanabe T. A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. p. 616-619. 5774961 https://doi.org/10.1109/APCCAS.2010.5774961
Lin, Zhen ; Dong, Yiping ; Li, Yan ; Watanabe, Takahiro. / A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. pp. 616-619
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