A hybrid architecture for efficient FPGA-based implementation of multilayer neural network

Zhen Lin; Yiping Dong; Yan Li; Takahiro Watanabe

doi:10.1109/APCCAS.2010.5774961

A hybrid architecture for efficient FPGA-based implementation of multilayer neural network

Zhen Lin^*, Yiping Dong, Yan Li, Takahiro Watanabe

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.

Original language	English
Title of host publication	Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages	616-619
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2010.5774961
Publication status	Published - 2010 Dec 1
Event	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia Duration: 2010 Dec 6 → 2010 Dec 9

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	10/12/6 → 10/12/9

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2010.5774961

Cite this

Lin, Z., Dong, Y., Li, Y., & Watanabe, T. (2010). A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (pp. 616-619). [5774961] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774961

A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. / Lin, Zhen; Dong, Yiping; Li, Yan et al.

Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 616-619 5774961 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, Z, Dong, Y, Li, Y & Watanabe, T 2010, A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. in Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010., 5774961, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 616-619, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 10/12/6. https://doi.org/10.1109/APCCAS.2010.5774961

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abstract = "This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.",

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A hybrid architecture for efficient FPGA-based implementation of multilayer neural network

Abstract

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ASJC Scopus subject areas

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