A hypothesis verification method using a regression tree for semiconductor yield analysis

Hidetaka Tsuda, Hidehiro Shirai, Masahiro Terabe, Kazuo Hashimoto, Ayumi Shinohara

Research output: Contribution to journalArticle

Abstract

Several researchers have reported on regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the root node do not indicate the hypothesized causes of a failure. We propose a method for verifying the hypothesized causes of a failure, which reduces the number of verification hypotheses. This method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying regression tree analysis separately to each set of analysis data, and merging and sorting the attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of regression tree analysis for semiconductor yield. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 183(3): 26-36, 2013; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22334

Original languageEnglish
Pages (from-to)26-36
Number of pages11
JournalElectrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
Volume183
Issue number3
DOIs
Publication statusPublished - 2013 May 1

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Keywords

  • attribute
  • failure cause identification.
  • hypothesis verification
  • regression tree analysis
  • semiconductor
  • yield analysis

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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