A hypothesis verification method using regression tree for semiconductor yield analysis

Hidetaka Tsuda, Hidehiro Shirai, Masahiro Terabe, Kazuo Hashimoto, Ayumi Shinohara

Research output: Contribution to journalArticle

2 Citations (Scopus)


Several researchers have reported the regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying the regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the route node do not indicate the hypothesized causes of failure. We propose a method for verifying the hypothesized causes of failure, which reduces the number of verification hypotheses. Our method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying the regression tree analysis separately to each set of analysis data, and merging and sorting attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of the regression tree analysis for semiconductor yield.

Original languageEnglish
Pages (from-to)1232-1239
Number of pages8
JournalIEEJ Transactions on Industry Applications
Issue number10
Publication statusPublished - 2011
Externally publishedYes



  • Attribute
  • Failure cause identification
  • Hypothesis verification
  • Regression tree analysis
  • Semiconductor
  • Yield analysis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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