A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

M. Fujii; K. Nii; H. Makino; S. Ohbayashi; M. Igarashi; T. Kawamura; M. Yokota; N. Tsuda; T. Yoshizawa; T. Tsutsui; N. Takeshita; N. Murata; T. Tanaka; T. Fujiwara; K. Asahina; M. Okada; K. Tomita; M. Takeuchi; H. Shinohara

doi:10.1109/ICMTS.2007.374469

A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

M. Fujii^*, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, H. Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

Original language	English
Title of host publication	2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings
Pages	131-134
Number of pages	4
DOIs	https://doi.org/10.1109/ICMTS.2007.374469
Publication status	Published - 2007
Externally published	Yes
Event	2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 - Bunkyo-ku, Japan Duration: 2007 Mar 19 → 2007 Mar 22

Publication series

Name	IEEE International Conference on Microelectronic Test Structures

Other

Other	2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
Country/Territory	Japan
City	Bunkyo-ku
Period	07/3/19 → 07/3/22

Keywords

Large-scale integration
Logic circuit fault diagnosis
SRAM
Yield optimization

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICMTS.2007.374469

Cite this

Fujii, M., Nii, K., Makino, H., Ohbayashi, S., Igarashi, M., Kawamura, T., Yokota, M., Tsuda, N., Yoshizawa, T., Tsutsui, T., Takeshita, N., Murata, N., Tanaka, T., Fujiwara, T., Asahina, K., Okada, M., Tomita, K., Takeuchi, M., & Shinohara, H. (2007). A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. In 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings (pp. 131-134). [4252419] (IEEE International Conference on Microelectronic Test Structures). https://doi.org/10.1109/ICMTS.2007.374469

A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. / Fujii, M.; Nii, K.; Makino, H. et al.

2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings. 2007. p. 131-134 4252419 (IEEE International Conference on Microelectronic Test Structures).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujii, M, Nii, K, Makino, H, Ohbayashi, S, Igarashi, M, Kawamura, T, Yokota, M, Tsuda, N, Yoshizawa, T, Tsutsui, T, Takeshita, N, Murata, N, Tanaka, T, Fujiwara, T, Asahina, K, Okada, M, Tomita, K, Takeuchi, M & Shinohara, H 2007, A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. in 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings., 4252419, IEEE International Conference on Microelectronic Test Structures, pp. 131-134, 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07, Bunkyo-ku, Japan, 07/3/19. https://doi.org/10.1109/ICMTS.2007.374469

Fujii M, Nii K, Makino H, Ohbayashi S, Igarashi M, Kawamura T et al. A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. In 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings. 2007. p. 131-134. 4252419. (IEEE International Conference on Microelectronic Test Structures). doi: 10.1109/ICMTS.2007.374469

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abstract = "We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.",

keywords = "Large-scale integration, Logic circuit fault diagnosis, SRAM, Yield optimization",

author = "M. Fujii and K. Nii and H. Makino and S. Ohbayashi and M. Igarashi and T. Kawamura and M. Yokota and N. Tsuda and T. Yoshizawa and T. Tsutsui and N. Takeshita and N. Murata and T. Tanaka and T. Fujiwara and K. Asahina and M. Okada and K. Tomita and M. Takeuchi and H. Shinohara",

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AU - Kawamura, T.

AU - Yokota, M.

AU - Tsuda, N.

AU - Yoshizawa, T.

AU - Tsutsui, T.

AU - Takeshita, N.

AU - Murata, N.

AU - Tanaka, T.

AU - Fujiwara, T.

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AB - We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

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A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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