A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

M. Fujii, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

Original languageEnglish
Title of host publicationIEEE International Conference on Microelectronic Test Structures
Pages131-134
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 - Bunkyo-ku, Japan
Duration: 2007 Mar 192007 Mar 22

Other

Other2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
CountryJapan
CityBunkyo-ku
Period07/3/1907/3/22

Fingerprint

Flip flop circuits
Random access storage
Static random access storage

Keywords

  • Large-scale integration
  • Logic circuit fault diagnosis
  • SRAM
  • Yield optimization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Fujii, M., Nii, K., Makino, H., Ohbayashi, S., Igarashi, M., Kawamura, T., ... Shinohara, H. (2007). A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. In IEEE International Conference on Microelectronic Test Structures (pp. 131-134). [4252419] https://doi.org/10.1109/ICMTS.2007.374469

A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. / Fujii, M.; Nii, K.; Makino, H.; Ohbayashi, S.; Igarashi, M.; Kawamura, T.; Yokota, M.; Tsuda, N.; Yoshizawa, T.; Tsutsui, T.; Takeshita, N.; Murata, N.; Tanaka, T.; Fujiwara, T.; Asahina, K.; Okada, M.; Tomita, K.; Takeuchi, M.; Shinohara, Hirofumi.

IEEE International Conference on Microelectronic Test Structures. 2007. p. 131-134 4252419.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujii, M, Nii, K, Makino, H, Ohbayashi, S, Igarashi, M, Kawamura, T, Yokota, M, Tsuda, N, Yoshizawa, T, Tsutsui, T, Takeshita, N, Murata, N, Tanaka, T, Fujiwara, T, Asahina, K, Okada, M, Tomita, K, Takeuchi, M & Shinohara, H 2007, A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. in IEEE International Conference on Microelectronic Test Structures., 4252419, pp. 131-134, 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07, Bunkyo-ku, Japan, 07/3/19. https://doi.org/10.1109/ICMTS.2007.374469
Fujii M, Nii K, Makino H, Ohbayashi S, Igarashi M, Kawamura T et al. A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. In IEEE International Conference on Microelectronic Test Structures. 2007. p. 131-134. 4252419 https://doi.org/10.1109/ICMTS.2007.374469
Fujii, M. ; Nii, K. ; Makino, H. ; Ohbayashi, S. ; Igarashi, M. ; Kawamura, T. ; Yokota, M. ; Tsuda, N. ; Yoshizawa, T. ; Tsutsui, T. ; Takeshita, N. ; Murata, N. ; Tanaka, T. ; Fujiwara, T. ; Asahina, K. ; Okada, M. ; Tomita, K. ; Takeuchi, M. ; Shinohara, Hirofumi. / A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology. IEEE International Conference on Microelectronic Test Structures. 2007. pp. 131-134
@inproceedings{302589d8194446d2b4012b8b652d1194,
title = "A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology",
abstract = "We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.",
keywords = "Large-scale integration, Logic circuit fault diagnosis, SRAM, Yield optimization",
author = "M. Fujii and K. Nii and H. Makino and S. Ohbayashi and M. Igarashi and T. Kawamura and M. Yokota and N. Tsuda and T. Yoshizawa and T. Tsutsui and N. Takeshita and N. Murata and T. Tanaka and T. Fujiwara and K. Asahina and M. Okada and K. Tomita and M. Takeuchi and Hirofumi Shinohara",
year = "2007",
doi = "10.1109/ICMTS.2007.374469",
language = "English",
isbn = "142440780X",
pages = "131--134",
booktitle = "IEEE International Conference on Microelectronic Test Structures",

}

TY - GEN

T1 - A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

AU - Fujii, M.

AU - Nii, K.

AU - Makino, H.

AU - Ohbayashi, S.

AU - Igarashi, M.

AU - Kawamura, T.

AU - Yokota, M.

AU - Tsuda, N.

AU - Yoshizawa, T.

AU - Tsutsui, T.

AU - Takeshita, N.

AU - Murata, N.

AU - Tanaka, T.

AU - Fujiwara, T.

AU - Asahina, K.

AU - Okada, M.

AU - Tomita, K.

AU - Takeuchi, M.

AU - Shinohara, Hirofumi

PY - 2007

Y1 - 2007

N2 - We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

AB - We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

KW - Large-scale integration

KW - Logic circuit fault diagnosis

KW - SRAM

KW - Yield optimization

UR - http://www.scopus.com/inward/record.url?scp=34548827050&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548827050&partnerID=8YFLogxK

U2 - 10.1109/ICMTS.2007.374469

DO - 10.1109/ICMTS.2007.374469

M3 - Conference contribution

SN - 142440780X

SN - 9781424407804

SP - 131

EP - 134

BT - IEEE International Conference on Microelectronic Test Structures

ER -