A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology

Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchl, Shigehisa Yamamoto, Hiromitsu Sugimoto & 1 others Hirofumi Shinohara

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Original languageEnglish
Pages (from-to)1338-1347
Number of pages10
JournalIEICE Transactions on Electronics
VolumeE91-C
Issue number8
DOIs
Publication statusPublished - 2008 Aug
Externally publishedYes

Fingerprint

Flip flop circuits
Random access storage
Static random access storage
Neutrons
Metals
Transistors

Keywords

  • Large-scale integration
  • Logic circuit fault diagnosis
  • SRAM
  • Yield optimization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology. / Fujii, Masako; Nii, Koji; Makino, Hiroshi; Ohbayashi, Shigeki; Igarashi, Motoshige; Kawamura, Takeshi; Yokota, Miho; Tsuda, Nobuhiro; Yoshizawa, Tomoaki; Tsutsui, Toshikazu; Takeshita, Naohiko; Murata, Naofumi; Tanaka, Tomohiro; Fujiwara, Takanari; Asahina, Kyoko; Okada, Masakazu; Tomita, Kazuo; Takeuchl, Masahiko; Yamamoto, Shigehisa; Sugimoto, Hiromitsu; Shinohara, Hirofumi.

In: IEICE Transactions on Electronics, Vol. E91-C, No. 8, 08.2008, p. 1338-1347.

Research output: Contribution to journalArticle

Fujii, M, Nii, K, Makino, H, Ohbayashi, S, Igarashi, M, Kawamura, T, Yokota, M, Tsuda, N, Yoshizawa, T, Tsutsui, T, Takeshita, N, Murata, N, Tanaka, T, Fujiwara, T, Asahina, K, Okada, M, Tomita, K, Takeuchl, M, Yamamoto, S, Sugimoto, H & Shinohara, H 2008, 'A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology', IEICE Transactions on Electronics, vol. E91-C, no. 8, pp. 1338-1347. https://doi.org/10.1093/ietele/e91-c.8.1338
Fujii, Masako ; Nii, Koji ; Makino, Hiroshi ; Ohbayashi, Shigeki ; Igarashi, Motoshige ; Kawamura, Takeshi ; Yokota, Miho ; Tsuda, Nobuhiro ; Yoshizawa, Tomoaki ; Tsutsui, Toshikazu ; Takeshita, Naohiko ; Murata, Naofumi ; Tanaka, Tomohiro ; Fujiwara, Takanari ; Asahina, Kyoko ; Okada, Masakazu ; Tomita, Kazuo ; Takeuchl, Masahiko ; Yamamoto, Shigehisa ; Sugimoto, Hiromitsu ; Shinohara, Hirofumi. / A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology. In: IEICE Transactions on Electronics. 2008 ; Vol. E91-C, No. 8. pp. 1338-1347.
@article{6651631ed3ec41b1a887a3ae00e25ead,
title = "A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology",
abstract = "We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.",
keywords = "Large-scale integration, Logic circuit fault diagnosis, SRAM, Yield optimization",
author = "Masako Fujii and Koji Nii and Hiroshi Makino and Shigeki Ohbayashi and Motoshige Igarashi and Takeshi Kawamura and Miho Yokota and Nobuhiro Tsuda and Tomoaki Yoshizawa and Toshikazu Tsutsui and Naohiko Takeshita and Naofumi Murata and Tomohiro Tanaka and Takanari Fujiwara and Kyoko Asahina and Masakazu Okada and Kazuo Tomita and Masahiko Takeuchl and Shigehisa Yamamoto and Hiromitsu Sugimoto and Hirofumi Shinohara",
year = "2008",
month = "8",
doi = "10.1093/ietele/e91-c.8.1338",
language = "English",
volume = "E91-C",
pages = "1338--1347",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "8",

}

TY - JOUR

T1 - A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology

AU - Fujii, Masako

AU - Nii, Koji

AU - Makino, Hiroshi

AU - Ohbayashi, Shigeki

AU - Igarashi, Motoshige

AU - Kawamura, Takeshi

AU - Yokota, Miho

AU - Tsuda, Nobuhiro

AU - Yoshizawa, Tomoaki

AU - Tsutsui, Toshikazu

AU - Takeshita, Naohiko

AU - Murata, Naofumi

AU - Tanaka, Tomohiro

AU - Fujiwara, Takanari

AU - Asahina, Kyoko

AU - Okada, Masakazu

AU - Tomita, Kazuo

AU - Takeuchl, Masahiko

AU - Yamamoto, Shigehisa

AU - Sugimoto, Hiromitsu

AU - Shinohara, Hirofumi

PY - 2008/8

Y1 - 2008/8

N2 - We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

AB - We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

KW - Large-scale integration

KW - Logic circuit fault diagnosis

KW - SRAM

KW - Yield optimization

UR - http://www.scopus.com/inward/record.url?scp=77953525119&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953525119&partnerID=8YFLogxK

U2 - 10.1093/ietele/e91-c.8.1338

DO - 10.1093/ietele/e91-c.8.1338

M3 - Article

VL - E91-C

SP - 1338

EP - 1347

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 8

ER -