A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Abstract

    Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.

    Original languageEnglish
    Title of host publication2018 19th International Symposium on Quality Electronic Design, ISQED 2018
    PublisherIEEE Computer Society
    Pages106-111
    Number of pages6
    Volume2018-March
    ISBN (Electronic)9781538612149
    DOIs
    Publication statusPublished - 2018 May 9
    Event19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States
    Duration: 2018 Mar 13 → 2018 Mar 14

    Other

    Other19th International Symposium on Quality Electronic Design, ISQED 2018
    CountryUnited States
    CitySanta Clara
    Period18/3/13 → 18/3/14

    Fingerprint

    Field programmable gate arrays (FPGA)
    Cryptography
    Program processors
    Hardware
    High level synthesis

    Keywords

    • FPGA
    • fully homomorphic encryption (FHE)
    • high-level synthesis (HLS)
    • loop optimization
    • number theoretic transform (NTT)

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

    Cite this

    Kawamura, K., Yanagisawa, M., & Togawa, N. (2018). A loop structure optimization targeting high-level synthesis of fast number theoretic transform. In 2018 19th International Symposium on Quality Electronic Design, ISQED 2018 (Vol. 2018-March, pp. 106-111). IEEE Computer Society. https://doi.org/10.1109/ISQED.2018.8357273

    A loop structure optimization targeting high-level synthesis of fast number theoretic transform. / Kawamura, Kazushi; Yanagisawa, Masao; Togawa, Nozomu.

    2018 19th International Symposium on Quality Electronic Design, ISQED 2018. Vol. 2018-March IEEE Computer Society, 2018. p. 106-111.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Kawamura, K, Yanagisawa, M & Togawa, N 2018, A loop structure optimization targeting high-level synthesis of fast number theoretic transform. in 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. vol. 2018-March, IEEE Computer Society, pp. 106-111, 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, United States, 18/3/13. https://doi.org/10.1109/ISQED.2018.8357273
    Kawamura K, Yanagisawa M, Togawa N. A loop structure optimization targeting high-level synthesis of fast number theoretic transform. In 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. Vol. 2018-March. IEEE Computer Society. 2018. p. 106-111 https://doi.org/10.1109/ISQED.2018.8357273
    Kawamura, Kazushi ; Yanagisawa, Masao ; Togawa, Nozomu. / A loop structure optimization targeting high-level synthesis of fast number theoretic transform. 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. Vol. 2018-March IEEE Computer Society, 2018. pp. 106-111
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