Abstract
Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.
| Original language | English |
|---|---|
| Title of host publication | 2018 19th International Symposium on Quality Electronic Design, ISQED 2018 |
| Publisher | IEEE Computer Society |
| Pages | 106-111 |
| Number of pages | 6 |
| Volume | 2018-March |
| ISBN (Electronic) | 9781538612149 |
| DOIs | |
| Publication status | Published - 2018 May 9 |
| Event | 19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States Duration: 2018 Mar 13 → 2018 Mar 14 |
Other
| Other | 19th International Symposium on Quality Electronic Design, ISQED 2018 |
|---|---|
| Country | United States |
| City | Santa Clara |
| Period | 18/3/13 → 18/3/14 |
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Keywords
- FPGA
- fully homomorphic encryption (FHE)
- high-level synthesis (HLS)
- loop optimization
- number theoretic transform (NTT)
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
Cite this
A loop structure optimization targeting high-level synthesis of fast number theoretic transform. / Kawamura, Kazushi; Yanagisawa, Masao; Togawa, Nozomu.
2018 19th International Symposium on Quality Electronic Design, ISQED 2018. Vol. 2018-March IEEE Computer Society, 2018. p. 106-111.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A loop structure optimization targeting high-level synthesis of fast number theoretic transform
AU - Kawamura, Kazushi
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2018/5/9
Y1 - 2018/5/9
N2 - Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.
AB - Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.
KW - FPGA
KW - fully homomorphic encryption (FHE)
KW - high-level synthesis (HLS)
KW - loop optimization
KW - number theoretic transform (NTT)
UR - http://www.scopus.com/inward/record.url?scp=85047948083&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85047948083&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2018.8357273
DO - 10.1109/ISQED.2018.8357273
M3 - Conference contribution
VL - 2018-March
SP - 106
EP - 111
BT - 2018 19th International Symposium on Quality Electronic Design, ISQED 2018
PB - IEEE Computer Society
ER -