Abstract
A low-bandwidth Integer Motion Estimation (IME) module is proposed for MPEG-2 to H.264 transcoding. Based on bandwidth reduction method proposed in Ref. 1), a ping-pang memory control scheme combined with Partial Sum of Absolute Differences (SAD) Variable Block Size Motion Estimation (VBSME) architecture are realized. Experiment results show bandwidth of the proposed architecture is 70.6% of H.264 regular IME (Level C+ scheme, 2 Macro Block (MB) stitched vertically), while the on-chip memory size is 11.7% of that.
| Original language | English |
|---|---|
| Pages (from-to) | 114-121 |
| Number of pages | 8 |
| Journal | IPSJ Transactions on System LSI Design Methodology |
| Volume | 2 |
| DOIs | |
| Publication status | Published - 2009 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
Cite this
A low bandwidth Integer Motion Estimation module for MPEG-2 to H.264 transcoding. / Wei, Xianghui; Ikenaga, Takeshi; Goto, Satoshi.
In: IPSJ Transactions on System LSI Design Methodology, Vol. 2, 2009, p. 114-121.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A low bandwidth Integer Motion Estimation module for MPEG-2 to H.264 transcoding
AU - Wei, Xianghui
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
PY - 2009
Y1 - 2009
N2 - A low-bandwidth Integer Motion Estimation (IME) module is proposed for MPEG-2 to H.264 transcoding. Based on bandwidth reduction method proposed in Ref. 1), a ping-pang memory control scheme combined with Partial Sum of Absolute Differences (SAD) Variable Block Size Motion Estimation (VBSME) architecture are realized. Experiment results show bandwidth of the proposed architecture is 70.6% of H.264 regular IME (Level C+ scheme, 2 Macro Block (MB) stitched vertically), while the on-chip memory size is 11.7% of that.
AB - A low-bandwidth Integer Motion Estimation (IME) module is proposed for MPEG-2 to H.264 transcoding. Based on bandwidth reduction method proposed in Ref. 1), a ping-pang memory control scheme combined with Partial Sum of Absolute Differences (SAD) Variable Block Size Motion Estimation (VBSME) architecture are realized. Experiment results show bandwidth of the proposed architecture is 70.6% of H.264 regular IME (Level C+ scheme, 2 Macro Block (MB) stitched vertically), while the on-chip memory size is 11.7% of that.
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U2 - 10.2197/ipsjtsldm.2.114
DO - 10.2197/ipsjtsldm.2.114
M3 - Article
AN - SCOPUS:79851486362
VL - 2
SP - 114
EP - 121
JO - IPSJ Transactions on System LSI Design Methodology
JF - IPSJ Transactions on System LSI Design Methodology
SN - 1882-6687
ER -