A low cost and high speed CSD-based symmetric transpose block FIR implementation

Jinghao Ye; Youhua Shi; Nozomu Togawa; Masao Yanagisawa

doi:10.1109/ASICON.2017.8252475

A low cost and high speed CSD-based symmetric transpose block FIR implementation

Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.

Original language	English
Title of host publication	Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
Editors	Yajie Qin, Zhiliang Hong, Ting-Ao Tang
Publisher	IEEE Computer Society
Pages	311-314
Number of pages	4
ISBN (Electronic)	9781509066247
DOIs	https://doi.org/10.1109/ASICON.2017.8252475
Publication status	Published - 2017 Jul 1
Event	12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China Duration: 2017 Oct 25 → 2017 Oct 28

Publication series

Name	Proceedings of International Conference on ASIC
Volume	2017-October
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Other

Other	12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
Country/Territory	China
City	Guiyang
Period	17/10/25 → 17/10/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ASICON.2017.8252475

Cite this

Ye, J., Shi, Y., Togawa, N., & Yanagisawa, M. (2017). A low cost and high speed CSD-based symmetric transpose block FIR implementation. In Y. Qin, Z. Hong, & T-A. Tang (Eds.), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (pp. 311-314). (Proceedings of International Conference on ASIC; Vol. 2017-October). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252475

A low cost and high speed CSD-based symmetric transpose block FIR implementation. / Ye, Jinghao; Shi, Youhua ; Togawa, Nozomu et al.

Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. ed. / Yajie Qin; Zhiliang Hong; Ting-Ao Tang. IEEE Computer Society, 2017. p. 311-314 (Proceedings of International Conference on ASIC; Vol. 2017-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ye, J, Shi, Y , Togawa, N & Yanagisawa, M 2017, A low cost and high speed CSD-based symmetric transpose block FIR implementation. in Y Qin, Z Hong & T-A Tang (eds), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Proceedings of International Conference on ASIC, vol. 2017-October, IEEE Computer Society, pp. 311-314, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, China, 17/10/25. https://doi.org/10.1109/ASICON.2017.8252475

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abstract = "In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.",

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AB - In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.

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A low cost and high speed CSD-based symmetric transpose block FIR implementation

Abstract

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ASJC Scopus subject areas

UN SDGs

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