A low cost and high speed CSD-based symmetric transpose block FIR implementation

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
PublisherIEEE Computer Society
Pages311-314
Number of pages4
Volume2017-October
ISBN (Electronic)9781509066247
DOIs
Publication statusPublished - 2018 Jan 8
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: 2017 Oct 252017 Oct 28

Other

Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
CountryChina
CityGuiyang
Period17/10/2517/10/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Ye, J., Shi, Y., Togawa, N., & Yanagisawa, M. (2018). A low cost and high speed CSD-based symmetric transpose block FIR implementation. In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (Vol. 2017-October, pp. 311-314). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252475