A low power 720p motion estimation processor with 3D stacked memory

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.

Original languageEnglish
Title of host publicationIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
PublisherIEEE Computer Society
Volume2015-January
EditionJanuary
DOIs
Publication statusPublished - 2015 Jan 7
Event2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico
Duration: 2014 Oct 62014 Oct 8

Other

Other2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
CountryMexico
CityPlaya del Carmen
Period14/10/614/10/8

Fingerprint

Motion estimation
Data storage equipment
Bandwidth
Memory architecture
Silicon
Data communication systems
Electric power utilization
Wire
Controllers

Keywords

  • 3DIC design
  • low power design
  • memory stacking
  • motion estimation processor

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Zhang, S., Zhou, J., Zhou, D., & Goto, S. (2015). A low power 720p motion estimation processor with 3D stacked memory. In IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC (January ed., Vol. 2015-January). [7004163] IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2014.7004163

A low power 720p motion estimation processor with 3D stacked memory. / Zhang, Shuping; Zhou, Jinjia; Zhou, Dajiang; Goto, Satoshi.

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. Vol. 2015-January January. ed. IEEE Computer Society, 2015. 7004163.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, S, Zhou, J, Zhou, D & Goto, S 2015, A low power 720p motion estimation processor with 3D stacked memory. in IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. January edn, vol. 2015-January, 7004163, IEEE Computer Society, 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, 14/10/6. https://doi.org/10.1109/VLSI-SoC.2014.7004163
Zhang S, Zhou J, Zhou D, Goto S. A low power 720p motion estimation processor with 3D stacked memory. In IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. January ed. Vol. 2015-January. IEEE Computer Society. 2015. 7004163 https://doi.org/10.1109/VLSI-SoC.2014.7004163
Zhang, Shuping ; Zhou, Jinjia ; Zhou, Dajiang ; Goto, Satoshi. / A low power 720p motion estimation processor with 3D stacked memory. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. Vol. 2015-January January. ed. IEEE Computer Society, 2015.
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