A low power 720p motion estimation processor with 3D stacked memory

Shuping Zhang; Jinjia Zhou; Dajiang Zhou; Satoshi Goto

doi:10.1109/VLSI-SoC.2014.7004163

A low power 720p motion estimation processor with 3D stacked memory

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto

Information, Production and Systems Research Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.

Original language	English
Title of host publication	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Publisher	IEEE Computer Society
Volume	2015-January
Edition	January
DOIs	https://doi.org/10.1109/VLSI-SoC.2014.7004163
Publication status	Published - 2015 Jan 7
Event	2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico Duration: 2014 Oct 6 → 2014 Oct 8

Other

Other	2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
Country/Territory	Mexico
City	Playa del Carmen
Period	14/10/6 → 14/10/8

Keywords

3DIC design
low power design
memory stacking
motion estimation processor

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2014.7004163

Cite this

Zhang, S, Zhou, J, Zhou, D & Goto, S 2015, A low power 720p motion estimation processor with 3D stacked memory. in IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC. January edn, vol. 2015-January, 7004163, IEEE Computer Society, 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, 14/10/6. https://doi.org/10.1109/VLSI-SoC.2014.7004163

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abstract = "In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.",

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N2 - In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.

AB - In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.

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A low power 720p motion estimation processor with 3D stacked memory

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Keywords

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