A low-power misprediction recovery mechanism

Jiongyao Ye, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance. Previous researches proposed dual (or multi) path execution methods attempt to reduce the misprediction penalty, but these methods are quite complex and high power consumption. Most of the reasons are due to simultaneously fetching and executing instructions from multiple. In this paper, we reduce branch misprediction penalties based on the balance between complexity, power, and performance. We present a novel technique - Decode Recovery Cache (DRC) - for reducing misprediction penalty, giving consideration to complexity and power consumption simultaneously. The DRC stores decoded instructions that are mispredicted. Then during subsequent mispredictions, a hit in the DRC can reduce the re-fill time of pipeline, and eliminate instruction re-fetch and its subsequent decoding. The bypassing of both re-fetching and re-decoding reduces processor power. Experimental results employing SPECint 2000 benchmark show that, using a processor with DRC, IPC value is significantly improved by 10.4% on average over the traditional processors and average power consumption is reduced by 62.6%, compared with dual Path Instruction Processing.

Original languageEnglish
Title of host publication1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
Pages209-212
Number of pages4
DOIs
Publication statusPublished - 2009
Event1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 - Shanghai
Duration: 2009 Nov 192009 Nov 21

Other

Other1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
CityShanghai
Period09/11/1909/11/21

Fingerprint

penalty
Recovery
Electric power utilization
instruction
Decoding
Pipelines
performance
Processing
Values

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Education

Cite this

Ye, J., & Watanabe, T. (2009). A low-power misprediction recovery mechanism. In 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 (pp. 209-212). [5397409] https://doi.org/10.1109/PRIMEASIA.2009.5397409

A low-power misprediction recovery mechanism. / Ye, Jiongyao; Watanabe, Takahiro.

1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009. 2009. p. 209-212 5397409.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ye, J & Watanabe, T 2009, A low-power misprediction recovery mechanism. in 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009., 5397409, pp. 209-212, 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009, Shanghai, 09/11/19. https://doi.org/10.1109/PRIMEASIA.2009.5397409
Ye J, Watanabe T. A low-power misprediction recovery mechanism. In 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009. 2009. p. 209-212. 5397409 https://doi.org/10.1109/PRIMEASIA.2009.5397409
Ye, Jiongyao ; Watanabe, Takahiro. / A low-power misprediction recovery mechanism. 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009. 2009. pp. 209-212
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