A low-power shared cache design with modified PID controller for efficient multicore embedded systems

Huatao Zhao, Jiongyao Ye, Takahiro Watanabe

Research output: Contribution to journalArticle

1 Citation (Scopus)


Nowadays, on-chip cache scales are oversized in multicore embedded systems, and those caches even consume half of the total energy debit. However, we observe that a large portion of cache banks are wasted, meaning that those banks are rarely used but consume a great deal of energy during their entire lifetime. In this paper, we propose a controllable shared last level cache (SLLC) scheme to dynamically trace cache bank demands for each thread. Thus, energy on useless banks can be largely saved. Specifically, we (1) propose an effective cache bank allocating policy to explore bank demands corresponding to executed applications, (2) discuss the interrelations between application locality change and bank demands for further energy saving and (3) represent a modified PID controller to generate optimal banks for each thread. Experimental results show that our controllable SLLC design can save on average 39.7 percent shared cache access energy over conventional cache, while its performance is slightly improved and additional hardware overhead is less than 0.6 percent.

Original languageEnglish
Pages (from-to)149-158
Number of pages10
JournalJournal of information processing
Publication statusPublished - 2019 Jan 1



  • Cache optimization
  • Chip multicore
  • Embedded system
  • Low power
  • PID control

ASJC Scopus subject areas

  • Computer Science(all)

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