A low-power shared cache design with modified PID controller for efficient multicore embedded systems

Huatao Zhao, Jiongyao Ye, Takahiro Watanabe

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Nowadays, on-chip cache scales are oversized in multicore embedded systems, and those caches even consume half of the total energy debit. However, we observe that a large portion of cache banks are wasted, meaning that those banks are rarely used but consume a great deal of energy during their entire lifetime. In this paper, we propose a controllable shared last level cache (SLLC) scheme to dynamically trace cache bank demands for each thread. Thus, energy on useless banks can be largely saved. Specifically, we (1) propose an effective cache bank allocating policy to explore bank demands corresponding to executed applications, (2) discuss the interrelations between application locality change and bank demands for further energy saving and (3) represent a modified PID controller to generate optimal banks for each thread. Experimental results show that our controllable SLLC design can save on average 39.7 percent shared cache access energy over conventional cache, while its performance is slightly improved and additional hardware overhead is less than 0.6 percent.

Original languageEnglish
Pages (from-to)149-158
Number of pages10
JournalJournal of information processing
Volume27
DOIs
Publication statusPublished - 2019 Jan 1

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Embedded systems
Controllers
Energy conservation
Hardware

Keywords

  • Cache optimization
  • Chip multicore
  • Embedded system
  • Low power
  • PID control

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

A low-power shared cache design with modified PID controller for efficient multicore embedded systems. / Zhao, Huatao; Ye, Jiongyao; Watanabe, Takahiro.

In: Journal of information processing, Vol. 27, 01.01.2019, p. 149-158.

Research output: Contribution to journalArticle

@article{1fd32347590d406986bf697d957e6011,
title = "A low-power shared cache design with modified PID controller for efficient multicore embedded systems",
abstract = "Nowadays, on-chip cache scales are oversized in multicore embedded systems, and those caches even consume half of the total energy debit. However, we observe that a large portion of cache banks are wasted, meaning that those banks are rarely used but consume a great deal of energy during their entire lifetime. In this paper, we propose a controllable shared last level cache (SLLC) scheme to dynamically trace cache bank demands for each thread. Thus, energy on useless banks can be largely saved. Specifically, we (1) propose an effective cache bank allocating policy to explore bank demands corresponding to executed applications, (2) discuss the interrelations between application locality change and bank demands for further energy saving and (3) represent a modified PID controller to generate optimal banks for each thread. Experimental results show that our controllable SLLC design can save on average 39.7 percent shared cache access energy over conventional cache, while its performance is slightly improved and additional hardware overhead is less than 0.6 percent.",
keywords = "Cache optimization, Chip multicore, Embedded system, Low power, PID control",
author = "Huatao Zhao and Jiongyao Ye and Takahiro Watanabe",
year = "2019",
month = "1",
day = "1",
doi = "10.2197/ipsjjip.27.149",
language = "English",
volume = "27",
pages = "149--158",
journal = "Journal of Information Processing",
issn = "0387-5806",
publisher = "Information Processing Society of Japan",

}

TY - JOUR

T1 - A low-power shared cache design with modified PID controller for efficient multicore embedded systems

AU - Zhao, Huatao

AU - Ye, Jiongyao

AU - Watanabe, Takahiro

PY - 2019/1/1

Y1 - 2019/1/1

N2 - Nowadays, on-chip cache scales are oversized in multicore embedded systems, and those caches even consume half of the total energy debit. However, we observe that a large portion of cache banks are wasted, meaning that those banks are rarely used but consume a great deal of energy during their entire lifetime. In this paper, we propose a controllable shared last level cache (SLLC) scheme to dynamically trace cache bank demands for each thread. Thus, energy on useless banks can be largely saved. Specifically, we (1) propose an effective cache bank allocating policy to explore bank demands corresponding to executed applications, (2) discuss the interrelations between application locality change and bank demands for further energy saving and (3) represent a modified PID controller to generate optimal banks for each thread. Experimental results show that our controllable SLLC design can save on average 39.7 percent shared cache access energy over conventional cache, while its performance is slightly improved and additional hardware overhead is less than 0.6 percent.

AB - Nowadays, on-chip cache scales are oversized in multicore embedded systems, and those caches even consume half of the total energy debit. However, we observe that a large portion of cache banks are wasted, meaning that those banks are rarely used but consume a great deal of energy during their entire lifetime. In this paper, we propose a controllable shared last level cache (SLLC) scheme to dynamically trace cache bank demands for each thread. Thus, energy on useless banks can be largely saved. Specifically, we (1) propose an effective cache bank allocating policy to explore bank demands corresponding to executed applications, (2) discuss the interrelations between application locality change and bank demands for further energy saving and (3) represent a modified PID controller to generate optimal banks for each thread. Experimental results show that our controllable SLLC design can save on average 39.7 percent shared cache access energy over conventional cache, while its performance is slightly improved and additional hardware overhead is less than 0.6 percent.

KW - Cache optimization

KW - Chip multicore

KW - Embedded system

KW - Low power

KW - PID control

UR - http://www.scopus.com/inward/record.url?scp=85062393241&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85062393241&partnerID=8YFLogxK

U2 - 10.2197/ipsjjip.27.149

DO - 10.2197/ipsjjip.27.149

M3 - Article

AN - SCOPUS:85062393241

VL - 27

SP - 149

EP - 158

JO - Journal of Information Processing

JF - Journal of Information Processing

SN - 0387-5806

ER -