A low-power soft error tolerant latch scheme

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

    Original languageEnglish
    Title of host publicationProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781479984831
    DOIs
    Publication statusPublished - 2016 Jul 19
    Event11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
    Duration: 2015 Nov 32015 Nov 6

    Other

    Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
    CountryChina
    CityChengdu
    Period15/11/315/11/6

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'A low-power soft error tolerant latch scheme'. Together they form a unique fingerprint.

  • Cite this

    Tajima, S., Shi, Y., Togawa, N., & Yanagisawa, M. (2016). A low-power soft error tolerant latch scheme. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7516885] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7516885