A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Qian Xie, Leona Okamura, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)

    Abstract

    In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bit-iter.

    Original languageEnglish
    Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    Pages298-301
    Number of pages4
    DOIs
    Publication statusPublished - 2011
    Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu
    Duration: 2011 Apr 252011 Apr 28

    Other

    Other2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    CityHsinchu
    Period11/4/2511/4/28

    Fingerprint

    Macros
    Decoding
    Throughput
    Parallel architectures
    Pulse code modulation
    Energy efficiency
    Clocks
    Pipelines

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Chen, Z., Peng, X., Zhao, X., Xie, Q., Okamura, L., Zhou, D., & Goto, S. (2011). A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 298-301). [5783634] https://doi.org/10.1109/VDAT.2011.5783634

    A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application. / Chen, Zhixiang; Peng, Xiao; Zhao, Xiongxin; Xie, Qian; Okamura, Leona; Zhou, Dajiang; Goto, Satoshi.

    Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 298-301 5783634.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Chen, Z, Peng, X, Zhao, X, Xie, Q, Okamura, L, Zhou, D & Goto, S 2011, A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783634, pp. 298-301, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, 11/4/25. https://doi.org/10.1109/VDAT.2011.5783634
    Chen Z, Peng X, Zhao X, Xie Q, Okamura L, Zhou D et al. A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 298-301. 5783634 https://doi.org/10.1109/VDAT.2011.5783634
    Chen, Zhixiang ; Peng, Xiao ; Zhao, Xiongxin ; Xie, Qian ; Okamura, Leona ; Zhou, Dajiang ; Goto, Satoshi. / A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application. Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. pp. 298-301
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