A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Kazumi Inoh, Takeshi Hamamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m2(7F2 with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages93-96
Number of pages4
Publication statusPublished - 2003
Externally publishedYes
Event2003 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2003 Jun 122003 Jun 14

Other

Other2003 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period03/6/1203/6/14

Fingerprint

Dynamic random access storage
Transistors
Data storage equipment
Threshold voltage
Specifications
Networks (circuits)
Temperature

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Ohsawa, T., Higashi, T., Fujita, K., Ikehashi, T., Kajiyama, T., Fukuzumi, Y., ... Hamamoto, T. (2003). A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 93-96)

A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's. / Ohsawa, Takashi; Higashi, Tomoki; Fujita, Katsuyuki; Ikehashi, Tamio; Kajiyama, Takeshi; Fukuzumi, Yoshiaki; Shino, Tomoaki; Yamada, Hiroaki; Nakajima, Hiroomi; Minami, Yoshihiro; Yamada, Takashi; Inoh, Kazumi; Hamamoto, Takeshi.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2003. p. 93-96.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ohsawa, T, Higashi, T, Fujita, K, Ikehashi, T, Kajiyama, T, Fukuzumi, Y, Shino, T, Yamada, H, Nakajima, H, Minami, Y, Yamada, T, Inoh, K & Hamamoto, T 2003, A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers. pp. 93-96, 2003 Symposium on VLSI Circuits, Kyoto, Japan, 03/6/12.
Ohsawa T, Higashi T, Fujita K, Ikehashi T, Kajiyama T, Fukuzumi Y et al. A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2003. p. 93-96
Ohsawa, Takashi ; Higashi, Tomoki ; Fujita, Katsuyuki ; Ikehashi, Tamio ; Kajiyama, Takeshi ; Fukuzumi, Yoshiaki ; Shino, Tomoaki ; Yamada, Hiroaki ; Nakajima, Hiroomi ; Minami, Yoshihiro ; Yamada, Takashi ; Inoh, Kazumi ; Hamamoto, Takeshi. / A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2003. pp. 93-96
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AU - Shino, Tomoaki

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