Intelligent sensing is an important application field of video coding. For the next generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified transform architecture for VVC standard that enables 1D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. In order to minimize the number of adders, the N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the logical computation of the VVC transforms. In addition, a pipeline operation is employed to achieve a high throughput rate of 32 samples per cycle. The experimental and synthesis results show that our proposal can save 16.96% area and 9.89% power consumption than the direct implementation by the multipliers. Moreover, this design can reduce the normalized area (NA) by at least 57.53% compared with other advanced works.