TY - GEN
T1 - A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard
AU - Yibo, Fan
AU - Jiro, Katto
AU - Heming, Sun
AU - Xiaoyang, Zeng
AU - Yixuan, Zeng
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported in part by the National Natural Science Foundation of China under Grant 61674041, in part by Alibaba Group through Alibaba Innovative Research (AIR) Program, in part by the STCSM under Grant 16XD1400300, in part by the pioneering project of academy for engineering and technology and Fudan-CIOMP joint fund.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/9
Y1 - 2019/9
N2 - Intelligent sensing is an important application field of video coding. For the next generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified transform architecture for VVC standard that enables 1D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. In order to minimize the number of adders, the N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the logical computation of the VVC transforms. In addition, a pipeline operation is employed to achieve a high throughput rate of 32 samples per cycle. The experimental and synthesis results show that our proposal can save 16.96% area and 9.89% power consumption than the direct implementation by the multipliers. Moreover, this design can reduce the normalized area (NA) by at least 57.53% compared with other advanced works.
AB - Intelligent sensing is an important application field of video coding. For the next generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified transform architecture for VVC standard that enables 1D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. In order to minimize the number of adders, the N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the logical computation of the VVC transforms. In addition, a pipeline operation is employed to achieve a high throughput rate of 32 samples per cycle. The experimental and synthesis results show that our proposal can save 16.96% area and 9.89% power consumption than the direct implementation by the multipliers. Moreover, this design can reduce the normalized area (NA) by at least 57.53% compared with other advanced works.
KW - DCTVIII
KW - DST-VII
KW - Versatile Video Coding
KW - transform
UR - http://www.scopus.com/inward/record.url?scp=85085159955&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85085159955&partnerID=8YFLogxK
U2 - 10.1109/SOCC46988.2019.1570548652
DO - 10.1109/SOCC46988.2019.1570548652
M3 - Conference contribution
AN - SCOPUS:85085159955
T3 - International System on Chip Conference
SP - 176
EP - 180
BT - Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
A2 - Zhao, Danella
A2 - Basu, Arindam
A2 - Bayoumi, Magdy
A2 - Hwee, Gwee Bah
A2 - Tong, Ge
A2 - Sridhar, Ramalingam
PB - IEEE Computer Society
T2 - 32nd IEEE International System on Chip Conference, SOCC 2019
Y2 - 3 September 2019 through 6 September 2019
ER -