Abstract
Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.
| Original language | English |
|---|---|
| Title of host publication | ASICON 2005: 2005 6th International Conference on ASIC, Proceedings |
| Pages | 1031-1034 |
| Number of pages | 4 |
| Volume | 2 |
| Publication status | Published - 2005 |
| Event | ASICON 2005: 2005 6th International Conference on ASIC - Shanghai Duration: 2005 Oct 24 → 2005 Oct 27 |
Other
| Other | ASICON 2005: 2005 6th International Conference on ASIC |
|---|---|
| City | Shanghai |
| Period | 05/10/24 → 05/10/27 |
Fingerprint
ASJC Scopus subject areas
- Engineering(all)
Cite this
A mixed design flow for FPGA prototyping of design with scan circuits. / Li, Lingfeng; Fajar, Eko; Kurimoto, Ken Ichi; Goto, Satoshi.
ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 2 2005. p. 1031-1034 1611505.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A mixed design flow for FPGA prototyping of design with scan circuits
AU - Li, Lingfeng
AU - Fajar, Eko
AU - Kurimoto, Ken Ichi
AU - Goto, Satoshi
PY - 2005
Y1 - 2005
N2 - Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.
AB - Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.
UR - http://www.scopus.com/inward/record.url?scp=33847281987&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33847281987&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33847281987
SN - 0780392108
SN - 9780780392106
VL - 2
SP - 1031
EP - 1034
BT - ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
ER -