Abstract
Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.
| Original language | English |
|---|---|
| Title of host publication | ASICON 2005: 2005 6th International Conference on ASIC, Proceedings |
| Pages | 1031-1034 |
| Number of pages | 4 |
| Volume | 2 |
| Publication status | Published - 2005 |
| Event | ASICON 2005: 2005 6th International Conference on ASIC - Shanghai Duration: 2005 Oct 24 → 2005 Oct 27 |
Other
| Other | ASICON 2005: 2005 6th International Conference on ASIC |
|---|---|
| City | Shanghai |
| Period | 05/10/24 → 05/10/27 |
ASJC Scopus subject areas
- Engineering(all)
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Cite this
Li, L., Fajar, E., Kurimoto, K. I., & Goto, S. (2005). A mixed design flow for FPGA prototyping of design with scan circuits. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings (Vol. 2, pp. 1031-1034). [1611505]