A mixed design flow for FPGA prototyping of design with scan circuits

Lingfeng Li, Eko Fajar, Ken Ichi Kurimoto, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.

Original languageEnglish
Title of host publicationASICON 2005: 2005 6th International Conference on ASIC, Proceedings
Pages1031-1034
Number of pages4
Volume2
Publication statusPublished - 2005
EventASICON 2005: 2005 6th International Conference on ASIC - Shanghai
Duration: 2005 Oct 242005 Oct 27

Other

OtherASICON 2005: 2005 6th International Conference on ASIC
CityShanghai
Period05/10/2405/10/27

Fingerprint

Field programmable gate arrays (FPGA)
Networks (circuits)
Application specific integrated circuits

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Li, L., Fajar, E., Kurimoto, K. I., & Goto, S. (2005). A mixed design flow for FPGA prototyping of design with scan circuits. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings (Vol. 2, pp. 1031-1034). [1611505]

A mixed design flow for FPGA prototyping of design with scan circuits. / Li, Lingfeng; Fajar, Eko; Kurimoto, Ken Ichi; Goto, Satoshi.

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 2 2005. p. 1031-1034 1611505.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, L, Fajar, E, Kurimoto, KI & Goto, S 2005, A mixed design flow for FPGA prototyping of design with scan circuits. in ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. vol. 2, 1611505, pp. 1031-1034, ASICON 2005: 2005 6th International Conference on ASIC, Shanghai, 05/10/24.
Li L, Fajar E, Kurimoto KI, Goto S. A mixed design flow for FPGA prototyping of design with scan circuits. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 2. 2005. p. 1031-1034. 1611505
Li, Lingfeng ; Fajar, Eko ; Kurimoto, Ken Ichi ; Goto, Satoshi. / A mixed design flow for FPGA prototyping of design with scan circuits. ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 2 2005. pp. 1031-1034
@inproceedings{2464f4327d6d44058fbc23c990eae882,
title = "A mixed design flow for FPGA prototyping of design with scan circuits",
abstract = "Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 {\%} of the development time is required when compared to manual process.",
author = "Lingfeng Li and Eko Fajar and Kurimoto, {Ken Ichi} and Satoshi Goto",
year = "2005",
language = "English",
isbn = "0780392108",
volume = "2",
pages = "1031--1034",
booktitle = "ASICON 2005: 2005 6th International Conference on ASIC, Proceedings",

}

TY - GEN

T1 - A mixed design flow for FPGA prototyping of design with scan circuits

AU - Li, Lingfeng

AU - Fajar, Eko

AU - Kurimoto, Ken Ichi

AU - Goto, Satoshi

PY - 2005

Y1 - 2005

N2 - Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.

AB - Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.

UR - http://www.scopus.com/inward/record.url?scp=33847281987&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847281987&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0780392108

SN - 9780780392106

VL - 2

SP - 1031

EP - 1034

BT - ASICON 2005: 2005 6th International Conference on ASIC, Proceedings

ER -