A new 7-transistor SRAM cell design with high read stability

Yen Hsiang Tseng, Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

    Original languageEnglish
    Title of host publication2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
    Pages43-47
    Number of pages5
    DOIs
    Publication statusPublished - 2010
    Event2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur
    Duration: 2010 Apr 122010 Apr 13

    Other

    Other2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
    CityKuala Lumpur
    Period10/4/1210/4/13

    Fingerprint

    Static random access storage
    Transistors
    Durability
    Data storage equipment

    Keywords

    • Static Noise Margin (SNM)
    • Static Random Access Memory (SRAM)

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Tseng, Y. H., Zhang, Y., Okamura, L., & Yoshihara, T. (2010). A new 7-transistor SRAM cell design with high read stability. In 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings (pp. 43-47). [5503104] https://doi.org/10.1109/ICEDSA.2010.5503104

    A new 7-transistor SRAM cell design with high read stability. / Tseng, Yen Hsiang; Zhang, Yimeng; Okamura, Leona; Yoshihara, Tsutomu.

    2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. p. 43-47 5503104.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tseng, YH, Zhang, Y, Okamura, L & Yoshihara, T 2010, A new 7-transistor SRAM cell design with high read stability. in 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings., 5503104, pp. 43-47, 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010, Kuala Lumpur, 10/4/12. https://doi.org/10.1109/ICEDSA.2010.5503104
    Tseng YH, Zhang Y, Okamura L, Yoshihara T. A new 7-transistor SRAM cell design with high read stability. In 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. p. 43-47. 5503104 https://doi.org/10.1109/ICEDSA.2010.5503104
    Tseng, Yen Hsiang ; Zhang, Yimeng ; Okamura, Leona ; Yoshihara, Tsutomu. / A new 7-transistor SRAM cell design with high read stability. 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. pp. 43-47
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