A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe; Takashi Ohsawa; Kiyofumi Sakurai; Tohru Furuyama

doi:10.1109/4.34069

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

Original language	English
Pages (from-to)	905-910
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/4.34069
Publication status	Published - 1989 Aug
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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