A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

Original languageEnglish
Pages (from-to)905-910
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number4
DOIs
Publication statusPublished - 1989
Externally publishedYes

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Delay circuits
Dynamic random access storage
Computer peripheral equipment
Networks (circuits)
Capacitance
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. / Watanabe, Yohji; Ohsawa, Takashi; Sakurai, Kiyofumi; Furuyama, Tohru.

In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, 1989, p. 905-910.

Research output: Contribution to journalArticle

Watanabe, Yohji ; Ohsawa, Takashi ; Sakurai, Kiyofumi ; Furuyama, Tohru. / A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. In: IEEE Journal of Solid-State Circuits. 1989 ; Vol. 24, No. 4. pp. 905-910.
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