A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe; Takashi Ohsawa; Kiyofumi Sakurai; Tohru Furuyama

doi:10.1109/4.34069

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

Research output: Contribution to journal › Article

11 Citations (Scopus)

Abstract

A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

Original language	English
Pages (from-to)	905-910
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/4.34069
Publication status	Published - 1989
Externally published	Yes

Fingerprint

Delay circuits

Dynamic random access storage

Computer peripheral equipment

Networks (circuits)

Capacitance

Data storage equipment

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Watanabe, Y., Ohsawa, T., Sakurai, K., & Furuyama, T. (1989). A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. IEEE Journal of Solid-State Circuits, 24(4), 905-910. https://doi.org/10.1109/4.34069

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. / Watanabe, Yohji; Ohsawa, Takashi; Sakurai, Kiyofumi; Furuyama, Tohru.

In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, 1989, p. 905-910.

Research output: Contribution to journal › Article

Watanabe, Y, Ohsawa, T, Sakurai, K & Furuyama, T 1989, 'A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s', IEEE Journal of Solid-State Circuits, vol. 24, no. 4, pp. 905-910. https://doi.org/10.1109/4.34069

Watanabe Y, Ohsawa T, Sakurai K, Furuyama T. A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. IEEE Journal of Solid-State Circuits. 1989;24(4):905-910. https://doi.org/10.1109/4.34069

Watanabe, Yohji ; Ohsawa, Takashi ; Sakurai, Kiyofumi ; Furuyama, Tohru. / A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. In: IEEE Journal of Solid-State Circuits. 1989 ; Vol. 24, No. 4. pp. 905-910.

@article{0eee540a43d04477a844ddbd776df081,

title = "A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s",

abstract = "A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.",

author = "Yohji Watanabe and Takashi Ohsawa and Kiyofumi Sakurai and Tohru Furuyama",

year = "1989",

doi = "10.1109/4.34069",

language = "English",

volume = "24",

pages = "905--910",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Sakurai, Kiyofumi

AU - Furuyama, Tohru

PY - 1989

Y1 - 1989

N2 - A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

AB - A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

UR - http://www.scopus.com/inward/record.url?scp=0024717978&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024717978&partnerID=8YFLogxK

U2 - 10.1109/4.34069

DO - 10.1109/4.34069

M3 - Article

VL - 24

SP - 905

EP - 910

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -

Access to Document

10.1109/4.34069