A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe; Takashi Ohsawa; Kiyofumi Sakurai; Tohru Furuyama

doi:10.1109/4.34069

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

Original language	English
Pages (from-to)	905-910
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/4.34069
Publication status	Published - 1989 Aug
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.34069

Fingerprint Dive into the research topics of 'A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s'. Together they form a unique fingerprint.

Cite this

@article{0eee540a43d04477a844ddbd776df081,

title = "A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM{\textquoteright}s",

abstract = "A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM{\textquoteright}s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.",

author = "Yohji Watanabe and Takashi Ohsawa and Kiyofumi Sakurai and Tohru Furuyama",

year = "1989",

month = aug,

doi = "10.1109/4.34069",

language = "English",

volume = "24",

pages = "905--910",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Sakurai, Kiyofumi

AU - Furuyama, Tohru

PY - 1989/8

Y1 - 1989/8

N2 - A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

AB - A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.

UR - http://www.scopus.com/inward/record.url?scp=0024717978&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024717978&partnerID=8YFLogxK

U2 - 10.1109/4.34069

DO - 10.1109/4.34069

M3 - Article

AN - SCOPUS:0024717978

VL - 24

SP - 905

EP - 910

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Cite this