Abstract
A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.
Original language | English |
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Pages (from-to) | 905-910 |
Number of pages | 6 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 24 |
Issue number | 4 |
DOIs | |
Publication status | Published - 1989 |
Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s. / Watanabe, Yohji; Ohsawa, Takashi; Sakurai, Kiyofumi; Furuyama, Tohru.
In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, 1989, p. 905-910.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s
AU - Watanabe, Yohji
AU - Ohsawa, Takashi
AU - Sakurai, Kiyofumi
AU - Furuyama, Tohru
PY - 1989
Y1 - 1989
N2 - A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.
AB - A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.
UR - http://www.scopus.com/inward/record.url?scp=0024717978&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0024717978&partnerID=8YFLogxK
U2 - 10.1109/4.34069
DO - 10.1109/4.34069
M3 - Article
AN - SCOPUS:0024717978
VL - 24
SP - 905
EP - 910
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 4
ER -