A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki; Takeshi Nakayama; Shin ichi Kobayashi; Natsuo Ajika; Makoto Ohi; Yasushi Terada; Hideaki Arima; Tsutomu Yoshihara

doi:10.1109/4.126547

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki^*, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

Original language	English
Pages (from-to)	583-588
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	4
DOIs	https://doi.org/10.1109/4.126547
Publication status	Published - 1992 Apr
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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abstract = "To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.",

author = "Yoshikazu Miyawaki and Takeshi Nakayama and Kobayashi, {Shin ichi} and Natsuo Ajika and Makoto Ohi and Yasushi Terada and Hideaki Arima and Tsutomu Yoshihara",

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AU - Miyawaki, Yoshikazu

AU - Nakayama, Takeshi

AU - Kobayashi, Shin ichi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1992/4

Y1 - 1992/4

N2 - To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

AB - To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

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A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Abstract

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