A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

Original languageEnglish
Pages (from-to)583-588
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number4
DOIs
Publication statusPublished - 1992 Apr
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Miyawaki, Y., Nakayama, T., Kobayashi, S. I., Ajika, N., Ohi, M., Terada, Y., Arima, H., & Yoshihara, T. (1992). A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories. IEEE Journal of Solid-State Circuits, 27(4), 583-588. https://doi.org/10.1109/4.126547