A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

Yoshikazu Miyawaki; Takeshi Nakayama; Shin ichi Kobayashi; Natsuo Ajika; Makoto Ohi; Yasushi Terada; Hideaki Arima; Tsutomu Yoshihara

A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

Yoshikazu Miyawaki^*, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

Original language	English
Title of host publication	91 Symp VLSI Circuits
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	85-86
Number of pages	2
Publication status	Published - 1991
Externally published	Yes
Event	1991 Symposium on VLSI Circuits - Oiso, Jpn Duration: 1991 May 30 → 1991 Jun 1

Other

Other	1991 Symposium on VLSI Circuits
City	Oiso, Jpn
Period	91/5/30 → 91/6/1

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs",

abstract = "The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.",

author = "Yoshikazu Miyawaki and Takeshi Nakayama and Kobayashi, {Shin ichi} and Natsuo Ajika and Makoto Ohi and Yasushi Terada and Hideaki Arima and Tsutomu Yoshihara",

year = "1991",

language = "English",

pages = "85--86",

booktitle = "91 Symp VLSI Circuits",

publisher = "Publ by IEEE",

note = "1991 Symposium on VLSI Circuits ; Conference date: 30-05-1991 Through 01-06-1991",

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T1 - A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

AU - Miyawaki, Yoshikazu

AU - Nakayama, Takeshi

AU - Kobayashi, Shin ichi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1991

Y1 - 1991

N2 - The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

AB - The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

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UR - http://www.scopus.com/inward/citedby.url?scp=0026372198&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026372198

SP - 85

EP - 86

BT - 91 Symp VLSI Circuits

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - 1991 Symposium on VLSI Circuits

Y2 - 30 May 1991 through 1 June 1991

ER -

A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

Abstract

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ASJC Scopus subject areas

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