A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

Yoshikazu Miyawaki, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

Original languageEnglish
Title of host publication91 Symp VLSI Circuits
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages85-86
Number of pages2
Publication statusPublished - 1991
Externally publishedYes
Event1991 Symposium on VLSI Circuits - Oiso, Jpn
Duration: 1991 May 301991 Jun 1

Other

Other1991 Symposium on VLSI Circuits
CityOiso, Jpn
Period91/5/3091/6/1

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Miyawaki, Y., Nakayama, T., Kobayashi, S. I., Ajika, N., Ohi, M., Terada, Y., Arima, H., & Yoshihara, T. (1991). A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs. In 91 Symp VLSI Circuits (pp. 85-86). Publ by IEEE.