A new hardware/software partitioning algorithm for DSP processor cores with two types of register files

Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohsuki

    Research output: Contribution to journalArticle

    Abstract

    This letter proposes a hardware/software partitioning algorithm for digital signal processor cores with two register files. Given a compiled assembly code and a timing constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of register files. Moreover the algorithm considers two or more types of functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which consider only type of functional units for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

    Original languageEnglish
    Pages (from-to)2802-2807
    Number of pages6
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE84-A
    Issue number11
    Publication statusPublished - 2001 Nov

    Fingerprint

    Hardware/software Partitioning
    Hardware
    Unit
    Digital Signal Processor
    Digital signal processors
    Execution Time
    Assign
    Penalty
    Timing
    Configuration
    Experimental Results
    Demonstrate

    Keywords

    • Digital signal processor
    • Hardware unit
    • Hardware/software cosynthesis
    • Hardware/software partitioning
    • Register file

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

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