A new self-test structure for at-speed test of crosstalk in SoC busses

Jun Yang; Chen Hu; Youhua Shi; Zhe Zhang; Longxing Shi

A new self-test structure for at-speed test of crosstalk in SoC busses

Jun Yang^*, Chen Hu, Youhua Shi, Zhe Zhang, Longxing Shi

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.

Original language	English
Pages	633-636
Number of pages	4
Publication status	Published - 2001
Externally published	Yes
Event	4th International Conference on ASIC Proceedings - Shanghai, China Duration: 2001 Oct 23 → 2001 Oct 25

Conference

Conference	4th International Conference on ASIC Proceedings
Country/Territory	China
City	Shanghai
Period	01/10/23 → 01/10/25

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "A new self-test structure for at-speed test of crosstalk in SoC busses",

abstract = "The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.",

author = "Jun Yang and Chen Hu and Youhua Shi and Zhe Zhang and Longxing Shi",

year = "2001",

language = "English",

pages = "633--636",

note = "4th International Conference on ASIC Proceedings ; Conference date: 23-10-2001 Through 25-10-2001",

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T1 - A new self-test structure for at-speed test of crosstalk in SoC busses

AU - Yang, Jun

AU - Hu, Chen

AU - Shi, Youhua

AU - Zhang, Zhe

AU - Shi, Longxing

PY - 2001

Y1 - 2001

N2 - The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.

AB - The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.

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UR - http://www.scopus.com/inward/citedby.url?scp=0035721045&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0035721045

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T2 - 4th International Conference on ASIC Proceedings

Y2 - 23 October 2001 through 25 October 2001

ER -

A new self-test structure for at-speed test of crosstalk in SoC busses

Abstract

Conference

ASJC Scopus subject areas

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