The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.
|Number of pages||4|
|Publication status||Published - 2001|
|Event||4th International Conference on ASIC Proceedings - Shanghai, China|
Duration: 2001 Oct 23 → 2001 Oct 25
|Conference||4th International Conference on ASIC Proceedings|
|Period||01/10/23 → 01/10/25|
ASJC Scopus subject areas