A new self-test structure for at-speed test of crosstalk in SoC busses

Jun Yang, Chen Hu, Youhua Shi, Zhe Zhang, Longxing Shi

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.

Original languageEnglish
Pages633-636
Number of pages4
Publication statusPublished - 2001 Dec 1
Externally publishedYes
Event4th International Conference on ASIC Proceedings - Shanghai, China
Duration: 2001 Oct 232001 Oct 25

Conference

Conference4th International Conference on ASIC Proceedings
CountryChina
CityShanghai
Period01/10/2301/10/25

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Yang, J., Hu, C., Shi, Y., Zhang, Z., & Shi, L. (2001). A new self-test structure for at-speed test of crosstalk in SoC busses. 633-636. Paper presented at 4th International Conference on ASIC Proceedings, Shanghai, China.