A new software for test logic optimization in DFT

Zhe Zhang; Chen Hu; Rui Li; Youhua Shi; Longxing Shi

A new software for test logic optimization in DFT

Zhe Zhang, Chen Hu, Rui Li, Youhua Shi, Longxing Shi

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

Original language	English
Pages	654-657
Number of pages	4
Publication status	Published - 2001 Dec 1
Externally published	Yes
Event	4th International Conference on ASIC Proceedings - Shanghai, China Duration: 2001 Oct 23 → 2001 Oct 25

Conference

Conference	4th International Conference on ASIC Proceedings
Country	China
City	Shanghai
Period	01/10/23 → 01/10/25

ASJC Scopus subject areas

Engineering(all)

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title = "A new software for test logic optimization in DFT",

abstract = "This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.",

author = "Zhe Zhang and Chen Hu and Rui Li and Youhua Shi and Longxing Shi",

year = "2001",

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AU - Zhang, Zhe

AU - Hu, Chen

AU - Li, Rui

AU - Shi, Youhua

AU - Shi, Longxing

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N2 - This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

AB - This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

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