A new software for test logic optimization in DFT

Zhe Zhang, Chen Hu, Rui Li, Youhua Shi, Longxing Shi

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

Original languageEnglish
Pages654-657
Number of pages4
Publication statusPublished - 2001 Dec 1
Externally publishedYes
Event4th International Conference on ASIC Proceedings - Shanghai, China
Duration: 2001 Oct 232001 Oct 25

Conference

Conference4th International Conference on ASIC Proceedings
CountryChina
CityShanghai
Period01/10/2301/10/25

ASJC Scopus subject areas

  • Engineering(all)

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