This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.
|Number of pages||4|
|Publication status||Published - 2001 Dec 1|
|Event||4th International Conference on ASIC Proceedings - Shanghai, China|
Duration: 2001 Oct 23 → 2001 Oct 25
|Conference||4th International Conference on ASIC Proceedings|
|Period||01/10/23 → 01/10/25|
ASJC Scopus subject areas