A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

Khanh N. Dang, Michael Conrad Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan Tu Tran

Research output: Contribution to journalArticle

Abstract

As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).

Original languageEnglish
Article number9044845
Pages (from-to)59571-59589
Number of pages19
JournalIEEE Access
Volume8
DOIs
Publication statusPublished - 2020

Keywords

  • 3D-ICs
  • error correction code
  • fault-detection
  • fault-tolerance
  • networks-on-chip
  • parity check
  • product code
  • through-silicon-via

ASJC Scopus subject areas

  • Computer Science(all)
  • Materials Science(all)
  • Engineering(all)

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