A non-iterative effective capacitance model for CMOS gate delay computing

Minglu Jiang; Qiang Li; Zhangcai Huang; Yasuaki Inoue

doi:10.1109/ICCCAS.2010.5581849

A non-iterative effective capacitance model for CMOS gate delay computing

Minglu Jiang^*, Qiang Li, Zhangcai Huang, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G _{ef f} which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear G_{ef f} equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for G_{ef f} calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

Original language	English
Title of host publication	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings
Pages	896-900
Number of pages	5
DOIs	https://doi.org/10.1109/ICCCAS.2010.5581849
Publication status	Published - 2010
Event	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Chengdu Duration: 2010 Jul 28 → 2010 Jul 30

Other

Other	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010
City	Chengdu
Period	10/7/28 → 10/7/30

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICCCAS.2010.5581849

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Jiang, M, Li, Q, Huang, Z & Inoue, Y 2010, A non-iterative effective capacitance model for CMOS gate delay computing. in 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings., 5581849, pp. 896-900, 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010, Chengdu, 10/7/28. https://doi.org/10.1109/ICCCAS.2010.5581849

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abstract = "In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.",

author = "Minglu Jiang and Qiang Li and Zhangcai Huang and Yasuaki Inoue",

year = "2010",

doi = "10.1109/ICCCAS.2010.5581849",

language = "English",

isbn = "9781424482238",

pages = "896--900",

booktitle = "2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings",

note = "2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 ; Conference date: 28-07-2010 Through 30-07-2010",

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T1 - A non-iterative effective capacitance model for CMOS gate delay computing

AU - Jiang, Minglu

AU - Li, Qiang

AU - Huang, Zhangcai

AU - Inoue, Yasuaki

PY - 2010

Y1 - 2010

N2 - In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

AB - In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

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SN - 9781424482238

SP - 896

EP - 900

BT - 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings

T2 - 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010

Y2 - 28 July 2010 through 30 July 2010

ER -

A non-iterative effective capacitance model for CMOS gate delay computing

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