A non-iterative effective capacitance model for CMOS gate delay computing

Minglu Jiang, Qiang Li, Zhangcai Huang, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

    Original languageEnglish
    Title of host publication2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings
    Pages896-900
    Number of pages5
    DOIs
    Publication statusPublished - 2010
    Event2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Chengdu
    Duration: 2010 Jul 282010 Jul 30

    Other

    Other2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010
    CityChengdu
    Period10/7/2810/7/30

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Jiang, M., Li, Q., Huang, Z., & Inoue, Y. (2010). A non-iterative effective capacitance model for CMOS gate delay computing. In 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings (pp. 896-900). [5581849] https://doi.org/10.1109/ICCCAS.2010.5581849