A non-iterative method for calculating the effective capacitance of cmos gates with interconnect load effect

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue

    Research output: Contribution to journalArticle


    Gate delay evaluation is always a vital concern for highperformance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective apacitance Ceff , which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff , a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

    Original languageEnglish
    Pages (from-to)1201-1209
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    Issue number5
    Publication statusPublished - 2011 May



    • Effective capacitance
    • Gate delay
    • Noniterative
    • Static timing analysis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

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