A novel charge recovery logic structure with complementary pass-transistor network

Jingyang Li; Yimeng Zhang; Tsutomu Yoshihara

doi:10.1109/ISOCC.2012.6406914

A novel charge recovery logic structure with complementary pass-transistor network

Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.

Original language	English
Title of host publication	ISOCC 2012 - 2012 International SoC Design Conference
Pages	17-20
Number of pages	4
DOIs	https://doi.org/10.1109/ISOCC.2012.6406914
Publication status	Published - 2012
Event	2012 International SoC Design Conference, ISOCC 2012 - Jeju Island Duration: 2012 Nov 4 → 2012 Nov 7

Other

Other	2012 International SoC Design Conference, ISOCC 2012
City	Jeju Island
Period	12/11/4 → 12/11/7

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Keywords

4-bit counter
Charge recovery logic
CPBL
low power

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Li, J., Zhang, Y., & Yoshihara, T. (2012). A novel charge recovery logic structure with complementary pass-transistor network. In ISOCC 2012 - 2012 International SoC Design Conference (pp. 17-20). [6406914] https://doi.org/10.1109/ISOCC.2012.6406914

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Access to Document

10.1109/ISOCC.2012.6406914