A novel charge recovery logic structure with complementary pass-transistor network

Jingyang Li; Yimeng Zhang; Tsutomu Yoshihara

doi:10.1109/ISOCC.2012.6406914

A novel charge recovery logic structure with complementary pass-transistor network

Jingyang Li^*, Yimeng Zhang, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.

Original language	English
Title of host publication	ISOCC 2012 - 2012 International SoC Design Conference
Pages	17-20
Number of pages	4
DOIs	https://doi.org/10.1109/ISOCC.2012.6406914
Publication status	Published - 2012
Event	2012 International SoC Design Conference, ISOCC 2012 - Jeju Island Duration: 2012 Nov 4 → 2012 Nov 7

Other

Other	2012 International SoC Design Conference, ISOCC 2012
City	Jeju Island
Period	12/11/4 → 12/11/7

Keywords

4-bit counter
Charge recovery logic
CPBL
low power

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC.2012.6406914

Cite this

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title = "A novel charge recovery logic structure with complementary pass-transistor network",

abstract = "This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.",

keywords = "4-bit counter, Charge recovery logic, CPBL, low power",

author = "Jingyang Li and Yimeng Zhang and Tsutomu Yoshihara",

year = "2012",

doi = "10.1109/ISOCC.2012.6406914",

language = "English",

isbn = "9781467329880",

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note = "2012 International SoC Design Conference, ISOCC 2012 ; Conference date: 04-11-2012 Through 07-11-2012",

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T1 - A novel charge recovery logic structure with complementary pass-transistor network

AU - Li, Jingyang

AU - Zhang, Yimeng

AU - Yoshihara, Tsutomu

PY - 2012

Y1 - 2012

N2 - This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.

AB - This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.

KW - 4-bit counter

KW - Charge recovery logic

KW - CPBL

KW - low power

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BT - ISOCC 2012 - 2012 International SoC Design Conference

T2 - 2012 International SoC Design Conference, ISOCC 2012

Y2 - 4 November 2012 through 7 November 2012

ER -

A novel charge recovery logic structure with complementary pass-transistor network

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Keywords

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