A novel floorplan representation with random contour corner selecting scheme

Xiaohao Gao, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Floorplanning has played a crucial role in the VLSI physical design process, while a lot of focus has been put on the representation methodologies for the floorplan optimization in the recent researches. In this work, we propose an efficient P-admissible representation, called random contour corner (RCC), for non-slicing floorplans. It depends on a two-section random code, representing the sequence and location of the blocks respectively. The objective is to improve both area and wire length. For the optimization procedure, we apply a simulated annealing (SA) algorithm. The method is quite simple and time efficient for implementation even on large-scale integration floorplans, and the run time complexity for the algorithm is O(nlogn). The experimental results show that our proposed method achieves promising results by comparing with some other representations (O-tree, B*-tree and TCG) on basic MCNC benchmark circuits.

Original languageEnglish
Title of host publicationIEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings
Pages552-556
Number of pages5
DOIs
Publication statusPublished - 2013
Event2013 1st IEEE TENCON Spring Conference, TENCONSpring 2013 - Sydney, NSW
Duration: 2013 Apr 172013 Apr 19

Other

Other2013 1st IEEE TENCON Spring Conference, TENCONSpring 2013
CitySydney, NSW
Period13/4/1713/4/19

Fingerprint

LSI circuits
Simulated annealing
Wire
Networks (circuits)

Keywords

  • Floorplan
  • layout
  • representation
  • VLSI

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Gao, X., & Yoshimura, T. (2013). A novel floorplan representation with random contour corner selecting scheme. In IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings (pp. 552-556). [6584506] https://doi.org/10.1109/TENCONSpring.2013.6584506

A novel floorplan representation with random contour corner selecting scheme. / Gao, Xiaohao; Yoshimura, Takeshi.

IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings. 2013. p. 552-556 6584506.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gao, X & Yoshimura, T 2013, A novel floorplan representation with random contour corner selecting scheme. in IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings., 6584506, pp. 552-556, 2013 1st IEEE TENCON Spring Conference, TENCONSpring 2013, Sydney, NSW, 13/4/17. https://doi.org/10.1109/TENCONSpring.2013.6584506
Gao X, Yoshimura T. A novel floorplan representation with random contour corner selecting scheme. In IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings. 2013. p. 552-556. 6584506 https://doi.org/10.1109/TENCONSpring.2013.6584506
Gao, Xiaohao ; Yoshimura, Takeshi. / A novel floorplan representation with random contour corner selecting scheme. IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings. 2013. pp. 552-556
@inproceedings{0b31deaa943c4bf18a60ea5392b3dc68,
title = "A novel floorplan representation with random contour corner selecting scheme",
abstract = "Floorplanning has played a crucial role in the VLSI physical design process, while a lot of focus has been put on the representation methodologies for the floorplan optimization in the recent researches. In this work, we propose an efficient P-admissible representation, called random contour corner (RCC), for non-slicing floorplans. It depends on a two-section random code, representing the sequence and location of the blocks respectively. The objective is to improve both area and wire length. For the optimization procedure, we apply a simulated annealing (SA) algorithm. The method is quite simple and time efficient for implementation even on large-scale integration floorplans, and the run time complexity for the algorithm is O(nlogn). The experimental results show that our proposed method achieves promising results by comparing with some other representations (O-tree, B*-tree and TCG) on basic MCNC benchmark circuits.",
keywords = "Floorplan, layout, representation, VLSI",
author = "Xiaohao Gao and Takeshi Yoshimura",
year = "2013",
doi = "10.1109/TENCONSpring.2013.6584506",
language = "English",
isbn = "9781467363495",
pages = "552--556",
booktitle = "IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings",

}

TY - GEN

T1 - A novel floorplan representation with random contour corner selecting scheme

AU - Gao, Xiaohao

AU - Yoshimura, Takeshi

PY - 2013

Y1 - 2013

N2 - Floorplanning has played a crucial role in the VLSI physical design process, while a lot of focus has been put on the representation methodologies for the floorplan optimization in the recent researches. In this work, we propose an efficient P-admissible representation, called random contour corner (RCC), for non-slicing floorplans. It depends on a two-section random code, representing the sequence and location of the blocks respectively. The objective is to improve both area and wire length. For the optimization procedure, we apply a simulated annealing (SA) algorithm. The method is quite simple and time efficient for implementation even on large-scale integration floorplans, and the run time complexity for the algorithm is O(nlogn). The experimental results show that our proposed method achieves promising results by comparing with some other representations (O-tree, B*-tree and TCG) on basic MCNC benchmark circuits.

AB - Floorplanning has played a crucial role in the VLSI physical design process, while a lot of focus has been put on the representation methodologies for the floorplan optimization in the recent researches. In this work, we propose an efficient P-admissible representation, called random contour corner (RCC), for non-slicing floorplans. It depends on a two-section random code, representing the sequence and location of the blocks respectively. The objective is to improve both area and wire length. For the optimization procedure, we apply a simulated annealing (SA) algorithm. The method is quite simple and time efficient for implementation even on large-scale integration floorplans, and the run time complexity for the algorithm is O(nlogn). The experimental results show that our proposed method achieves promising results by comparing with some other representations (O-tree, B*-tree and TCG) on basic MCNC benchmark circuits.

KW - Floorplan

KW - layout

KW - representation

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=84883705743&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883705743&partnerID=8YFLogxK

U2 - 10.1109/TENCONSpring.2013.6584506

DO - 10.1109/TENCONSpring.2013.6584506

M3 - Conference contribution

SN - 9781467363495

SP - 552

EP - 556

BT - IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings

ER -