A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder

Wen Ji, Makoto Hamaminato, Hiroshi Nakayama, Satoshi Goto

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2 Citations (Scopus)

Abstract

In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite-Second Generation) application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm. The approximation theoretically shows that the offset value is mainly dependent on the difference between the two most unreliable inputs from the bit nodes and the algorithm proposed can adjust the offset value according to the inputs during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15dB gain under the same Bit Error Rate (BER) performance, compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case.

Original languageEnglish
Pages (from-to)1394-1398
Number of pages5
JournalUnknown Journal
Publication statusPublished - 2010

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ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

Ji, W., Hamaminato, M., Nakayama, H., & Goto, S. (2010). A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder. Unknown Journal, 1394-1398.