A novel hardware method to implement a routing algorithm onto network on chip

Yiping Dong; Hua Zhang; Zhen Lin; Takahiro Watanabe

doi:10.1109/ICCCAS.2010.5581857

A novel hardware method to implement a routing algorithm onto network on chip

Yiping Dong^*, Hua Zhang, Zhen Lin, Takahiro Watanabe

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destination-tag method for router design. We simulate and evaluate the router and NoC with proposed method in terms of circuit resource, latency and throughput. The results indicate that the NoC architecture with proposed method is effective in reducing circuit resource, latency and increasing throughput.

Original language	English
Title of host publication	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings
Pages	852-856
Number of pages	5
DOIs	https://doi.org/10.1109/ICCCAS.2010.5581857
Publication status	Published - 2010 Nov 19
Event	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Chengdu, China Duration: 2010 Jul 28 → 2010 Jul 30

Publication series

Name	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings

Conference

Conference	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010
Country/Territory	China
City	Chengdu
Period	10/7/28 → 10/7/30

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICCCAS.2010.5581857

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Dong, Y., Zhang, H., Lin, Z., & Watanabe, T. (2010). A novel hardware method to implement a routing algorithm onto network on chip. In 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings (pp. 852-856). [5581857] (2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings). https://doi.org/10.1109/ICCCAS.2010.5581857

A novel hardware method to implement a routing algorithm onto network on chip. / Dong, Yiping; Zhang, Hua; Lin, Zhen et al.

2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings. 2010. p. 852-856 5581857 (2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y, Zhang, H, Lin, Z & Watanabe, T 2010, A novel hardware method to implement a routing algorithm onto network on chip. in 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings., 5581857, 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings, pp. 852-856, 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010, Chengdu, China, 10/7/28. https://doi.org/10.1109/ICCCAS.2010.5581857

Dong Y, Zhang H, Lin Z, Watanabe T. A novel hardware method to implement a routing algorithm onto network on chip. In 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings. 2010. p. 852-856. 5581857. (2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings). doi: 10.1109/ICCCAS.2010.5581857

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abstract = "Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destination-tag method for router design. We simulate and evaluate the router and NoC with proposed method in terms of circuit resource, latency and throughput. The results indicate that the NoC architecture with proposed method is effective in reducing circuit resource, latency and increasing throughput.",

author = "Yiping Dong and Hua Zhang and Zhen Lin and Takahiro Watanabe",

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AB - Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destination-tag method for router design. We simulate and evaluate the router and NoC with proposed method in terms of circuit resource, latency and throughput. The results indicate that the NoC architecture with proposed method is effective in reducing circuit resource, latency and increasing throughput.

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A novel hardware method to implement a routing algorithm onto network on chip

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