A novel hetero-junction Tunnel-FET using Semiconducting silicide-Silicon contact and its scalability

Yan Wu*, Hiroyuki Hasegawa, Kuniyuki Kakushima, Kenji Ohmori, Takanobu Watanabe, Akira Nishiyama, Nobuyuki Sugii, Hitoshi Wakabayashi, Kazuo Tsutsui, Yoshinori Kataoka, Kenji Natori, Keisaku Yamada, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

21 Citations (Scopus)


A new type of silicon-based Tunneling FET (TFET) using semiconducting silicide Mg2Si/Si hetero-junction as source-channel structure is proposed and the device simulation has been presented. With narrow bandgap of silicide and the conduction and valence band discontinuous at the hetero-junction, larger drain current and smaller subthreshold swing than those of Si homo-junction TFET can be obtained. Structural optimization study reveals that low Si channel impurity concentration and the alignment of the gate electrode edge to the hetero-junction lead to better performance of the TFET. Scaling of the gate length increases the off-state leakage current, however, the drain voltage (Vd) reduction in accordance with the gate scaling suppresses the phenomenon, keeping its high drivability.

Original languageEnglish
Pages (from-to)899-904
Number of pages6
JournalMicroelectronics Reliability
Issue number5
Publication statusPublished - 2014 May

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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