A novel model for computing the effective capacitance of CMOS gates with interconnect loads

Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao

    Research output: Contribution to journalArticle

    6 Citations (Scopus)

    Abstract

    In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

    Original languageEnglish
    Pages (from-to)2562-2568
    Number of pages7
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE88-A
    Issue number10
    DOIs
    Publication statusPublished - 2005 Oct

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    Keywords

    • CMOS inverter
    • Effective capacitance
    • Interconnect loads
    • Static timing analysis, gate delay

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

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