A novel process for fabrication of gated silicon field emitter array taking advantage of ion bombardment retarded etching

A novel process for the fabrication of a gated silicon field emitter array is proposed. The process involves complete self-alignment of gate electrodes taking advantage of ion bombardment retarded etching. The ion-irradiated regions serve as masks for subsequent silicon etching resulting in the formation of tabletop structures. The structures are suitable for both the formation of pyramidal emitters and the arrangement of gate electrodes adjacent to each emitter. We integrate this silicon etching into a self-align process for the fabrication of gated emitter array. The emission characteristics of 100 emitters are tested, and the emission at a gate voltage of 30 V is detected. The results indicate that the proposed process is applicable to the fabrication of gated silicon emitters.