A novel SRAM structure for leakage power suppression in 45nm technology

Sui Huang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully conside. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] (2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

    Original languageEnglish
    Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
    Pages1070-1074
    Number of pages5
    DOIs
    Publication statusPublished - 2008
    Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province
    Duration: 2008 May 252008 May 27

    Other

    Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
    CityXiamen, Fujian Province
    Period08/5/2508/5/27

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

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