A novel structure of energy efficiency charge recovery logic

Yimeng Zhang, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

    Original languageEnglish
    Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
    Pages133-136
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai
    Duration: 2010 Jun 212010 Jun 23

    Other

    Other1st International Conference on Green Circuits and Systems, ICGCS 2010
    CityShanghai
    Period10/6/2110/6/23

    Keywords

    • AC power supply
    • Charge-recovery logic
    • Low energy dissipation

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Zhang, Y., Okamura, L., Huang, M., & Yoshihara, T. (2010). A novel structure of energy efficiency charge recovery logic. In 1st International Conference on Green Circuits and Systems, ICGCS 2010 (pp. 133-136). [5543082] https://doi.org/10.1109/ICGCS.2010.5543082