A numerical analysis of a CMOS image sensor with a simple fixed-pattern-noise-reduction technology

Kazuya Yonemoto, Hirofumi Sumi, Yoshikazu Ohba, Hiroshi Kawarada

Research output: Contribution to journalArticle

Abstract

A 1/3-inch 640 × 480-pixel CMOS image sensor was developed using a simple fixed-pattern-noise-reduction technology with a five-transistor pixel circuit and a low input-voltage I-V converter. In this report, we show the effectiveness of a low input-voltage I-V converter with a current-mirror circuit in improving the amplification ratio and linearity of a pixel circuit. The dependence of the pixel signal characteristics on the parameters of the pixel transistors was also analyzed. In a five-transistor pixel circuit, the threshold voltage of the X-Y addressing transistor affects the amplitude and level of the readout pulse. This report also contains analysis of the mechanism of the X-Y addressing transistor, illustrating the concept behind the selection of the threshold voltage.

Original languageEnglish
Pages (from-to)670-678
Number of pages9
JournalKyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers
Volume56
Issue number4
Publication statusPublished - 2002 Apr
Externally publishedYes

Fingerprint

Noise abatement
Image sensors
Numerical analysis
Pixels
Transistors
Networks (circuits)
Threshold voltage
Electric potential
Amplification
Mirrors

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Electronic, Optical and Magnetic Materials

Cite this

A numerical analysis of a CMOS image sensor with a simple fixed-pattern-noise-reduction technology. / Yonemoto, Kazuya; Sumi, Hirofumi; Ohba, Yoshikazu; Kawarada, Hiroshi.

In: Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers, Vol. 56, No. 4, 04.2002, p. 670-678.

Research output: Contribution to journalArticle

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