A parallel algorithm for constructing binary decision diagrams

Shinji Kimura, Edmund M. Clarke

Research output: Chapter in Book/Report/Conference proceedingConference contribution

42 Citations (Scopus)

Abstract

A parallel algorithm for constructing binary decision diagrams is described. The algorithms treats binary decision graphs as minimal finite automata. The automation for a Boolean fucntion with AND as its main operation (OR operation) is obtained by forming the intersection (union) of the regular sets associated with its operands. The union and intersection operations are implemented by a product construction on the minimal automata for the regular sets. After each product construction step the automaton must be reminimized. The parallel algorithm is designed so that it is possible to find the minimal representations for several Boolean operations in parallel. The level of each operation is determined. Operations at the same level can be performed in parallel without any communication between processors. If there are relatively few operations in one level, then the product generation step is divided into several suboperations and the results are merged.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages220-223
Number of pages4
ISBN (Print)O81862079X
Publication statusPublished - 1990 Sep
Externally publishedYes
EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
Duration: 1990 Sep 171990 Sep 19

Other

OtherProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period90/9/1790/9/19

Fingerprint

Binary decision diagrams
Parallel algorithms
Finite automata
Automation
Communication

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kimura, S., & Clarke, E. M. (1990). A parallel algorithm for constructing binary decision diagrams. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 220-223). Piscataway, NJ, United States: Publ by IEEE.

A parallel algorithm for constructing binary decision diagrams. / Kimura, Shinji; Clarke, Edmund M.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Piscataway, NJ, United States : Publ by IEEE, 1990. p. 220-223.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kimura, S & Clarke, EM 1990, A parallel algorithm for constructing binary decision diagrams. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, Piscataway, NJ, United States, pp. 220-223, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 90/9/17.
Kimura S, Clarke EM. A parallel algorithm for constructing binary decision diagrams. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Piscataway, NJ, United States: Publ by IEEE. 1990. p. 220-223
Kimura, Shinji ; Clarke, Edmund M. / A parallel algorithm for constructing binary decision diagrams. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Piscataway, NJ, United States : Publ by IEEE, 1990. pp. 220-223
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