### Abstract

A parallel algorithm for constructing binary decision diagrams is described. The algorithms treats binary decision graphs as minimal finite automata. The automation for a Boolean fucntion with AND as its main operation (OR operation) is obtained by forming the intersection (union) of the regular sets associated with its operands. The union and intersection operations are implemented by a product construction on the minimal automata for the regular sets. After each product construction step the automaton must be reminimized. The parallel algorithm is designed so that it is possible to find the minimal representations for several Boolean operations in parallel. The level of each operation is determined. Operations at the same level can be performed in parallel without any communication between processors. If there are relatively few operations in one level, then the product generation step is divided into several suboperations and the results are merged.

Original language | English |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |

Place of Publication | Piscataway, NJ, United States |

Publisher | Publ by IEEE |

Pages | 220-223 |

Number of pages | 4 |

ISBN (Print) | O81862079X |

Publication status | Published - 1990 Sep |

Externally published | Yes |

Event | Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA Duration: 1990 Sep 17 → 1990 Sep 19 |

### Other

Other | Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 |
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City | Cambridge, MA, USA |

Period | 90/9/17 → 90/9/19 |

### Fingerprint

### ASJC Scopus subject areas

- Hardware and Architecture
- Electrical and Electronic Engineering

### Cite this

*Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors*(pp. 220-223). Piscataway, NJ, United States: Publ by IEEE.

**A parallel algorithm for constructing binary decision diagrams.** / Kimura, Shinji; Clarke, Edmund M.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors.*Publ by IEEE, Piscataway, NJ, United States, pp. 220-223, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 90/9/17.

}

TY - GEN

T1 - A parallel algorithm for constructing binary decision diagrams

AU - Kimura, Shinji

AU - Clarke, Edmund M.

PY - 1990/9

Y1 - 1990/9

N2 - A parallel algorithm for constructing binary decision diagrams is described. The algorithms treats binary decision graphs as minimal finite automata. The automation for a Boolean fucntion with AND as its main operation (OR operation) is obtained by forming the intersection (union) of the regular sets associated with its operands. The union and intersection operations are implemented by a product construction on the minimal automata for the regular sets. After each product construction step the automaton must be reminimized. The parallel algorithm is designed so that it is possible to find the minimal representations for several Boolean operations in parallel. The level of each operation is determined. Operations at the same level can be performed in parallel without any communication between processors. If there are relatively few operations in one level, then the product generation step is divided into several suboperations and the results are merged.

AB - A parallel algorithm for constructing binary decision diagrams is described. The algorithms treats binary decision graphs as minimal finite automata. The automation for a Boolean fucntion with AND as its main operation (OR operation) is obtained by forming the intersection (union) of the regular sets associated with its operands. The union and intersection operations are implemented by a product construction on the minimal automata for the regular sets. After each product construction step the automaton must be reminimized. The parallel algorithm is designed so that it is possible to find the minimal representations for several Boolean operations in parallel. The level of each operation is determined. Operations at the same level can be performed in parallel without any communication between processors. If there are relatively few operations in one level, then the product generation step is divided into several suboperations and the results are merged.

UR - http://www.scopus.com/inward/record.url?scp=0025486860&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025486860&partnerID=8YFLogxK

M3 - Conference contribution

SN - O81862079X

SP - 220

EP - 223

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

PB - Publ by IEEE

CY - Piscataway, NJ, United States

ER -