A parallel LSI architecture for LDPC decoder improving message-passing schedule

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently, (ii) The proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages5099-5102
Number of pages4
Publication statusPublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos
Duration: 2006 May 212006 May 24

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CityKos
Period06/5/2106/5/24

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T., & Goto, S. (2006). A parallel LSI architecture for LDPC decoder improving message-passing schedule. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 5099-5102). [1693779]