A parallel LSI architecture for LDPC decoder improving message-passing schedule

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently, (ii) The proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages5099-5102
Number of pages4
Publication statusPublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos
Duration: 2006 May 212006 May 24

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CityKos
Period06/5/2106/5/24

Fingerprint

Message passing
Hardware
Iterative decoding
Decoding
Throughput

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T., & Goto, S. (2006). A parallel LSI architecture for LDPC decoder improving message-passing schedule. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 5099-5102). [1693779]

A parallel LSI architecture for LDPC decoder improving message-passing schedule. / Shimizu, Kazunori; Ishikawa, Tatsuyuki; Togawa, Nozomu; Ikenaga, Takeshi; Goto, Satoshi.

Proceedings - IEEE International Symposium on Circuits and Systems. 2006. p. 5099-5102 1693779.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shimizu, K, Ishikawa, T, Togawa, N, Ikenaga, T & Goto, S 2006, A parallel LSI architecture for LDPC decoder improving message-passing schedule. in Proceedings - IEEE International Symposium on Circuits and Systems., 1693779, pp. 5099-5102, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 06/5/21.
Shimizu K, Ishikawa T, Togawa N, Ikenaga T, Goto S. A parallel LSI architecture for LDPC decoder improving message-passing schedule. In Proceedings - IEEE International Symposium on Circuits and Systems. 2006. p. 5099-5102. 1693779
Shimizu, Kazunori ; Ishikawa, Tatsuyuki ; Togawa, Nozomu ; Ikenaga, Takeshi ; Goto, Satoshi. / A parallel LSI architecture for LDPC decoder improving message-passing schedule. Proceedings - IEEE International Symposium on Circuits and Systems. 2006. pp. 5099-5102
@inproceedings{0271a3e70d484f74aea35b1f52319a9c,
title = "A parallel LSI architecture for LDPC decoder improving message-passing schedule",
abstract = "This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently, (ii) The proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead.",
author = "Kazunori Shimizu and Tatsuyuki Ishikawa and Nozomu Togawa and Takeshi Ikenaga and Satoshi Goto",
year = "2006",
language = "English",
isbn = "0780393902",
pages = "5099--5102",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - A parallel LSI architecture for LDPC decoder improving message-passing schedule

AU - Shimizu, Kazunori

AU - Ishikawa, Tatsuyuki

AU - Togawa, Nozomu

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2006

Y1 - 2006

N2 - This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently, (ii) The proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead.

AB - This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently, (ii) The proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead.

UR - http://www.scopus.com/inward/record.url?scp=34547334311&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547334311&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0780393902

SN - 9780780393905

SP - 5099

EP - 5102

BT - Proceedings - IEEE International Symposium on Circuits and Systems

ER -