A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Pages1736-1739
    Number of pages4
    DOIs
    Publication statusPublished - 2013
    Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing
    Duration: 2013 May 192013 May 23

    Other

    Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    CityBeijing
    Period13/5/1913/5/23

    Fingerprint

    Scheduling
    High level synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Kawamura, K., Tanaka, S., Yanagisawa, M., & Togawa, N. (2013). A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1736-1739). [6572200] https://doi.org/10.1109/ISCAS.2013.6572200

    A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. / Kawamura, Kazushi; Tanaka, Sho; Yanagisawa, Masao; Togawa, Nozomu.

    Proceedings - IEEE International Symposium on Circuits and Systems. 2013. p. 1736-1739 6572200.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kawamura, K, Tanaka, S, Yanagisawa, M & Togawa, N 2013, A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. in Proceedings - IEEE International Symposium on Circuits and Systems., 6572200, pp. 1736-1739, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, 13/5/19. https://doi.org/10.1109/ISCAS.2013.6572200
    Kawamura K, Tanaka S, Yanagisawa M, Togawa N. A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. In Proceedings - IEEE International Symposium on Circuits and Systems. 2013. p. 1736-1739. 6572200 https://doi.org/10.1109/ISCAS.2013.6572200
    Kawamura, Kazushi ; Tanaka, Sho ; Yanagisawa, Masao ; Togawa, Nozomu. / A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. Proceedings - IEEE International Symposium on Circuits and Systems. 2013. pp. 1736-1739
    @inproceedings{d53e5fb137dd4dd18aef11cd3411bd04,
    title = "A partial redundant fault-secure high-level synthesis algorithm for RDR architectures",
    abstract = "In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52{\%} compared with the conventional approach.",
    author = "Kazushi Kawamura and Sho Tanaka and Masao Yanagisawa and Nozomu Togawa",
    year = "2013",
    doi = "10.1109/ISCAS.2013.6572200",
    language = "English",
    isbn = "9781467357609",
    pages = "1736--1739",
    booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

    }

    TY - GEN

    T1 - A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

    AU - Kawamura, Kazushi

    AU - Tanaka, Sho

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2013

    Y1 - 2013

    N2 - In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

    AB - In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

    UR - http://www.scopus.com/inward/record.url?scp=84883434768&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84883434768&partnerID=8YFLogxK

    U2 - 10.1109/ISCAS.2013.6572200

    DO - 10.1109/ISCAS.2013.6572200

    M3 - Conference contribution

    AN - SCOPUS:84883434768

    SN - 9781467357609

    SP - 1736

    EP - 1739

    BT - Proceedings - IEEE International Symposium on Circuits and Systems

    ER -