A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

Lian Zeng, Tieyuan Pan, Xin Jiang, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As the technology of semiconductor continues to develop, hundreds of cores will be deployed on a signal die in the future Chip-Multiprocessors (CMPs) design. So Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide high performance. The network performance depends critically on the performance of routing algorithm. This paper proposes a novel adaptive routing in 3D NoC which can solve congestion not only in the intra-layers but also in inter-layers. Simulation results show that our proposed method significantly achieves the performance improvement compared with other transitional routing algorithms.

Original languageEnglish
Title of host publicationIEEE Region 10 Annual International Conference, Proceedings/TENCON
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2016-January
ISBN (Print)9781479986415
DOIs
Publication statusPublished - 2016 Jan 5
Event35th IEEE Region 10 Conference, TENCON 2015 - Macau, Macao
Duration: 2015 Nov 12015 Nov 4

Other

Other35th IEEE Region 10 Conference, TENCON 2015
CountryMacao
CityMacau
Period15/11/115/11/4

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Keywords

  • 3D network-on-chip
  • Adaptive routing
  • congestion-balance
  • path diversity

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Zeng, L., Pan, T., Jiang, X., & Watanabe, T. (2016). A performance enhanced adaptive routing algorithm for 3D Network-on-Chips. In IEEE Region 10 Annual International Conference, Proceedings/TENCON (Vol. 2016-January). [7373036] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.2015.7373036