A performance enhanced dual-switch Network-on-Chip architecture

Lian Zeng; Takahiro Watanabe

doi:10.1109/ASPDAC.2015.7058983

A performance enhanced dual-switch Network-on-Chip architecture

Lian Zeng, Takahiro Watanabe

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-74
Number of pages	6
ISBN (Print)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058983
Publication status	Published - 2015 Mar 11
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: 2015 Jan 19 → 2015 Jan 22

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country	Japan
City	Chiba
Period	15/1/19 → 15/1/22

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modelling and Simulation

Access to Document

10.1109/ASPDAC.2015.7058983

Fingerprint Dive into the research topics of 'A performance enhanced dual-switch Network-on-Chip architecture'. Together they form a unique fingerprint.

Cite this

Zeng, L., & Watanabe, T. (2015). A performance enhanced dual-switch Network-on-Chip architecture. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 69-74). [7058983] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058983

Zeng, L & Watanabe, T 2015, A performance enhanced dual-switch Network-on-Chip architecture. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058983, Institute of Electrical and Electronics Engineers Inc., pp. 69-74, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15/1/19. https://doi.org/10.1109/ASPDAC.2015.7058983

@inproceedings{f009141c940d4b53bedaa7087bcdb9f3,

title = "A performance enhanced dual-switch Network-on-Chip architecture",

abstract = "Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.",

author = "Lian Zeng and Takahiro Watanabe",

year = "2015",

month = mar,

day = "11",

doi = "10.1109/ASPDAC.2015.7058983",

language = "English",

isbn = "9781479977925",

pages = "69--74",

booktitle = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 ; Conference date: 19-01-2015 Through 22-01-2015",

}

TY - GEN

T1 - A performance enhanced dual-switch Network-on-Chip architecture

AU - Zeng, Lian

AU - Watanabe, Takahiro

PY - 2015/3/11

Y1 - 2015/3/11

N2 - Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

AB - Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

UR - http://www.scopus.com/inward/record.url?scp=84926460619&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84926460619&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2015.7058983

DO - 10.1109/ASPDAC.2015.7058983

M3 - Conference contribution

AN - SCOPUS:84926460619

SN - 9781479977925

SP - 69

EP - 74

BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Y2 - 19 January 2015 through 22 January 2015

ER -