A performance enhanced dual-switch Network-on-Chip architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

Original languageEnglish
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages69-74
Number of pages6
ISBN (Print)9781479977925
DOIs
Publication statusPublished - 2015 Mar 11
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: 2015 Jan 192015 Jan 22

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period15/1/1915/1/22

Fingerprint

Network Performance
Network performance
Switch
Switches
Packet Routing
Latency
Throughput
Output
Experimental Results
Design
Architecture
Network on chip
Network-on-chip
System-on-chip

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

Cite this

Zeng, L., & Watanabe, T. (2015). A performance enhanced dual-switch Network-on-Chip architecture. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 69-74). [7058983] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058983

A performance enhanced dual-switch Network-on-Chip architecture. / Zeng, Lian; Watanabe, Takahiro.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 69-74 7058983.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zeng, L & Watanabe, T 2015, A performance enhanced dual-switch Network-on-Chip architecture. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058983, Institute of Electrical and Electronics Engineers Inc., pp. 69-74, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15/1/19. https://doi.org/10.1109/ASPDAC.2015.7058983
Zeng L, Watanabe T. A performance enhanced dual-switch Network-on-Chip architecture. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 69-74. 7058983 https://doi.org/10.1109/ASPDAC.2015.7058983
Zeng, Lian ; Watanabe, Takahiro. / A performance enhanced dual-switch Network-on-Chip architecture. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 69-74
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