A performance enhanced dual-switch network-on-chip architecture

Lian Zeng, Xin Jiang, Takahiro Watanabe

Research output: Contribution to journalArticle

Abstract

With rapid progress in semiconductor technology, Network-on-Chip (NoC) becomes an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. The delay of router and packets contention can significantly affect network latency and throughput. As the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing DSA design, we can make utmost use of idle output ports to reduce packets contention delay, meanwhile, without increasing router delay. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power and area overhead.

Original languageEnglish
Pages (from-to)85-94
Number of pages10
JournalIPSJ Transactions on System LSI Design Methodology
Volume8
DOIs
Publication statusPublished - 2015 Feb 1

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Switches
Network performance
Routers
Throughput
Semiconductor materials
Network-on-chip
System-on-chip

Keywords

  • Dual-switch
  • Network-on-chip
  • Performance enhanced

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

A performance enhanced dual-switch network-on-chip architecture. / Zeng, Lian; Jiang, Xin; Watanabe, Takahiro.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 8, 01.02.2015, p. 85-94.

Research output: Contribution to journalArticle

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