A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.