A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.

Original languageEnglish
Title of host publication25th PCS Proceedings
Subtitle of host publicationPicture Coding Symposium 2006, PCS2006
Publication statusPublished - 2006 Dec 1
Event25th PCS: Picture Coding Symposium 2006, PCS2006 - Beijing, China
Duration: 2006 Apr 242006 Apr 26

Publication series

Name25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006
Volume2006

Conference

Conference25th PCS: Picture Coding Symposium 2006, PCS2006
CountryChina
CityBeijing
Period06/4/2406/4/26

Keywords

  • H.264/AVC
  • VLSI architecture
  • Variable block size motion estimation

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Liu, Z., Song, Y., Ikenaga, T., & Goto, S. (2006). A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC. In 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006 (25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006; Vol. 2006).