A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

H. Koike, Takashi Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages317-320
Number of pages4
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore
Duration: 2013 Nov 112013 Nov 13

Other

Other2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
CitySingapore
Period13/11/1113/11/13

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Keywords

  • Flip-flop
  • MPU
  • MTJ
  • Nonvolatile
  • Power gating

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Koike, H., Ohsawa, T., Ikeda, S., Hanyu, T., Ohno, H., Endoh, T., Sakimura, N., Nebashi, R., Tsuji, Y., Morioka, A., Miura, S., Honjo, H., & Sugibayashi, T. (2013). A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop. In Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 (pp. 317-320). [6691046] https://doi.org/10.1109/ASSCC.2013.6691046