A power-saved 1Gbps irregular LDPC decoder based on simplified min-sum algorithm

Qi Wang, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper we proposed a fully-parallel irregular LDPC decoder which uses only registers to store the temporary intrinsic messages. Our decoder adopts a simplified min-sum algorithm to reduce the hardware implementation complexity and area, and due to the factor modification we achieve a negligible performance loss compared with the general min-sum algorithm. Considering reducing the power consumption, we also propose a power-saved strategy according to which the message evolution will halt as the parity-check condition is satisfied. This strategy will save us higher than 50% power under good channel condition. The synthesis result in 0.18μm CMOS technology shows our decoder for (648,540) irregular LDPC code achieves high throughput (1 Gbps) with 9.0ns latency.

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu
Duration: 2007 Apr 252007 Apr 27

Other

Other2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CityHsinchu
Period07/4/2507/4/27

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Wang, Q., Shimizu, K., Ikenaga, T., & Goto, S. (2007). A power-saved 1Gbps irregular LDPC decoder based on simplified min-sum algorithm. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239411] https://doi.org/10.1109/VDAT.2007.373219