A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

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Abstract

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

Original languageEnglish
Pages (from-to)2562-2563
Number of pages2
JournalIEEE Transactions on Electron Devices
Volume34
Issue number12
DOIs
Publication statusPublished - 1987
Externally publishedYes

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Photomasks
Metallizing
Fabrication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

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title = "A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area",
abstract = "A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.",
author = "Noriyoshi Yamauchi",
year = "1987",
doi = "10.1109/T-ED.1987.23351",
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journal = "IEEE Transactions on Electron Devices",
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publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

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AB - A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

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