A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

Noriyoshi Yamauchi

Research output: Contribution to journal › Article

Abstract

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

Original languageEnglish
Pages (from-to)2562-2563
Number of pages2
JournalIEEE Transactions on Electron Devices
Volume34
Issue number12
DOIs
Publication statusPublished - 1987
Externally publishedYes

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Photomasks
Metallizing
Fabrication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area. / Yamauchi, Noriyoshi.

In: IEEE Transactions on Electron Devices, Vol. 34, No. 12, 1987, p. 2562-2563.

Research output: Contribution to journal › Article

Yamauchi, N 1987, 'A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area', IEEE Transactions on Electron Devices, vol. 34, no. 12, pp. 2562-2563. https://doi.org/10.1109/T-ED.1987.23351
Yamauchi N. A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area. IEEE Transactions on Electron Devices. 1987;34(12):2562-2563. https://doi.org/10.1109/T-ED.1987.23351
Yamauchi, Noriyoshi. / A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area. In: IEEE Transactions on Electron Devices. 1987 ; Vol. 34, No. 12. pp. 2562-2563.
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