A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

Noriyoshi Yamauchi

doi:10.1109/T-ED.1987.23351

A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

Noriyoshi Yamauchi

Research output: Contribution to journal › Article › peer-review

Abstract

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

Original language	English
Pages (from-to)	2562-2563
Number of pages	2
Journal	IEEE Transactions on Electron Devices
Volume	34
Issue number	12
DOIs	https://doi.org/10.1109/T-ED.1987.23351
Publication status	Published - 1987
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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abstract = "A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.",

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