A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a process-variation-aware low-latency and multi-scenario high-level synthesis algorithm targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.

    Original languageEnglish
    Title of host publicationInternational System on Chip Conference
    PublisherIEEE Computer Society
    Pages7-12
    Number of pages6
    Volume2016-February
    ISBN (Print)9781467390934
    DOIs
    Publication statusPublished - 2016 Feb 12
    Event28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
    Duration: 2015 Sep 82015 Sep 11

    Other

    Other28th IEEE International System on Chip Conference, SOCC 2015
    CountryChina
    CityBeijing
    Period15/9/815/9/11

    Fingerprint

    Scheduling
    High level synthesis

    Keywords

    • hdr architecture
    • high-level synthesis
    • interconnection delay
    • process variation
    • scenario

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

    Cite this

    Igawa, K., Shi, Y., Yanagisawa, M., & Togawa, N. (2016). A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. In International System on Chip Conference (Vol. 2016-February, pp. 7-12). [7406898] IEEE Computer Society. https://doi.org/10.1109/SOCC.2015.7406898

    A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. / Igawa, Koki; Shi, Youhua; Yanagisawa, Masao; Togawa, Nozomu.

    International System on Chip Conference. Vol. 2016-February IEEE Computer Society, 2016. p. 7-12 7406898.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Igawa, K, Shi, Y, Yanagisawa, M & Togawa, N 2016, A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. in International System on Chip Conference. vol. 2016-February, 7406898, IEEE Computer Society, pp. 7-12, 28th IEEE International System on Chip Conference, SOCC 2015, Beijing, China, 15/9/8. https://doi.org/10.1109/SOCC.2015.7406898
    Igawa, Koki ; Shi, Youhua ; Yanagisawa, Masao ; Togawa, Nozomu. / A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. International System on Chip Conference. Vol. 2016-February IEEE Computer Society, 2016. pp. 7-12
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